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authorDavid Virag <virag.david003@gmail.com>2021-12-06 16:31:20 +0100
committerSylwester Nawrocki <s.nawrocki@samsung.com>2021-12-19 23:39:01 +0100
commit45bd8166a1d821eb8fada3092514a7c8543f537c (patch)
tree21b82526d09b2cd62e0a475d354627a3a0d841eb /drivers/platform/x86/intel/int3472/intel_skl_int3472_tps68470.c
parentc703a2f44cce4693c8d974ed1f583143261d81c1 (diff)
downloadlinux-45bd8166a1d821eb8fada3092514a7c8543f537c.tar.bz2
clk: samsung: Add initial Exynos7885 clock driver
This is an initial implementation adding basic clocks, such as UART, USI, I2C, WDT, ect. and their parent clocks. It is heavily based on the Exynos850 clock driver at 'drivers/clk/samsung/clk-exynos850.c' which was made by Sam Protsenko, thus the copyright and author lines were kept. Bus clocks are enabled by default as well to avoid hangs while trying to access CMU registers. Only the parts of CMU_TOP needed for CMU_CORE and CMU_PERI, a bit of CMU_CORE, and most of CMU_PERI is implemented as of now. Signed-off-by: David Virag <virag.david003@gmail.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20211206153124.427102-7-virag.david003@gmail.com
Diffstat (limited to 'drivers/platform/x86/intel/int3472/intel_skl_int3472_tps68470.c')
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