diff options
| author | Icenowy Zheng <icenowy@aosc.io> | 2018-03-16 22:02:09 +0800 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2018-03-27 15:07:49 +0200 |
| commit | 35817d34bd07b4e1cd597e054fa2bd9c9c111aab (patch) | |
| tree | 4e0c17938c4a90cff2b3f1dbe127d5760629b7d8 /drivers/pinctrl/sunxi/pinctrl-sunxi.h | |
| parent | 29dfc6bbcc5e1ef7ce1008c4713387efb8f567d2 (diff) | |
| download | linux-35817d34bd07b4e1cd597e054fa2bd9c9c111aab.tar.bz2 | |
pinctrl: sunxi: change irq_bank_base to irq_bank_map
The Allwinner H6 SoC have its pin controllers with the first IRQ-capable
GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5.
Change the current code that uses IRQ bank base to a IRQ bank map, in
order to support the case that holes exist among IRQ banks.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/sunxi/pinctrl-sunxi.h')
| -rw-r--r-- | drivers/pinctrl/sunxi/pinctrl-sunxi.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index 466840d886f6..4a892e7dde66 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -110,7 +110,7 @@ struct sunxi_pinctrl_desc { int npins; unsigned pin_base; unsigned irq_banks; - unsigned irq_bank_base; + const unsigned int *irq_bank_map; bool irq_read_needs_mux; bool disable_strict_mode; }; @@ -265,7 +265,10 @@ static inline u32 sunxi_pull_offset(u16 pin) static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u8 bank) { - return desc->irq_bank_base + bank; + if (!desc->irq_bank_map) + return bank; + else + return desc->irq_bank_map[bank]; } static inline u32 sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc *desc, |