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authorGeert Uytterhoeven <geert+renesas@glider.be>2018-12-12 19:50:36 +0100
committerGeert Uytterhoeven <geert+renesas@glider.be>2019-04-02 09:57:55 +0200
commitefca8da0c5fcc7f5617bab769faa595f7efdc593 (patch)
treeffc46103917cdcd8733992376567ecf34d97839d /drivers/pinctrl/sh-pfc/sh_pfc.h
parent01ff33a3ea57a7abf486e48a8d4d62435964038c (diff)
downloadlinux-efca8da0c5fcc7f5617bab769faa595f7efdc593.tar.bz2
pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro
Currently the PINMUX_CFG_REG() macro must be followed by initialization data, specifying all enum IDs. Hence the macro itself does not know anything about the enum IDs, preventing the macro from performing any validation on it. Make the macro accept the enum IDs as a parameter, and update all users. Note that array data enclosed by curly braces cannot be passed to a macro as a parameter, hence the enum IDs are wrapped using a new macro GROUPS(). No functional changes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/pinctrl/sh-pfc/sh_pfc.h')
-rw-r--r--drivers/pinctrl/sh-pfc/sh_pfc.h14
1 files changed, 9 insertions, 5 deletions
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 754e325d0bdb..3848c104543d 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -115,20 +115,24 @@ struct pinmux_cfg_reg {
const u8 *var_field_width;
};
+#define GROUP(...) __VA_ARGS__
+
/*
* Describe a config register consisting of several fields of the same width
* - name: Register name (unused, for documentation purposes only)
* - r: Physical register address
* - r_width: Width of the register (in bits)
* - f_width: Width of the fixed-width register fields (in bits)
- * This macro must be followed by initialization data: For each register field
- * (from left to right, i.e. MSB to LSB), 2^f_width enum IDs must be specified,
- * one for each possible combination of the register field bit values.
+ * - ids: For each register field (from left to right, i.e. MSB to LSB),
+ * 2^f_width enum IDs must be specified, one for each possible
+ * combination of the register field bit values, all wrapped using
+ * the GROUP() macro.
*/
-#define PINMUX_CFG_REG(name, r, r_width, f_width) \
+#define PINMUX_CFG_REG(name, r, r_width, f_width, ids) \
.reg = r, .reg_width = r_width, \
.field_width = f_width + BUILD_BUG_ON_ZERO(r_width % f_width), \
- .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])
+ .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) \
+ { ids }
/*
* Describe a config register consisting of several fields of different widths