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author | Linus Torvalds <torvalds@linux-foundation.org> | 2020-08-09 12:52:28 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2020-08-09 12:52:28 -0700 |
commit | 9420f1ce01869409d78901c3e036b2c437cbc6b8 (patch) | |
tree | ce371cca5922398c811f6a8072aed10343c2594d /drivers/pinctrl/pinctrl-rza1.c | |
parent | dec1fbbc1d7c46aed9fc1d3ee1f7f4fc04d6ed51 (diff) | |
parent | 7ee193e2dda3f48b692fad46ab9df90e99e7b811 (diff) | |
download | linux-9420f1ce01869409d78901c3e036b2c437cbc6b8.tar.bz2 |
Merge tag 'pinctrl-v5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of the pin control changes for the v5.9 kernel
series:
Core changes:
- The GPIO patch "gpiolib: Introduce for_each_requested_gpio_in_range()
macro" was put in an immutable branch and merged into the pinctrl
tree as well. We see these changes also here.
- Improved debug output for pins used as GPIO.
New drivers:
- Ocelot Sparx5 SoC driver.
- Intel Emmitsburg SoC subdriver.
- Intel Tiger Lake-H SoC subdriver.
- Qualcomm PM660 SoC subdriver.
- Renesas SH-PFC R8A774E1 subdriver.
Driver improvements:
- Linear improvement and cleanups of the Intel drivers for
Cherryview, Lynxpoint, Baytrail etc. Improved locking among other
things.
- Renesas SH-PFC has added support for RPC pins, groups, and
functions to r8a77970 and r8a77980.
- The newere Freescale (now NXP) i.MX8 pin controllers have been
modularized. This is driven by the Google Android GKI initiative I
think.
- Open drain support for pins on the Qualcomm IPQ4019.
- The Ingenic driver can handle both edges IRQ detection.
- A big slew of documentation fixes all over the place.
- A few irqchip template conversions by yours truly.
* tag 'pinctrl-v5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (107 commits)
dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC
pinctrl: stmfx: Use irqchip template
pinctrl: amd: Use irqchip template
pinctrl: mediatek: fix build for tristate changes
pinctrl: samsung: Use bank name as irqchip name
pinctrl: core: print gpio in pins debugfs file
pinctrl: mediatek: add mt6779 eint support
pinctrl: mediatek: add pinctrl support for MT6779 SoC
pinctrl: mediatek: avoid virtual gpio trying to set reg
pinctrl: mediatek: update pinmux definitions for mt6779
pinctrl: stm32: use the hwspin_lock_timeout_in_atomic() API
pinctrl: mcp23s08: Use irqchip template
pinctrl: sx150x: Use irqchip template
dt-bindings: ingenic,pinctrl: Support pinmux/pinconf nodes
pinctrl: intel: Add Intel Emmitsburg pin controller support
pinctl: ti: iodelay: Replace HTTP links with HTTPS ones
Revert "gpio: omap: handle pin config bias flags"
pinctrl: single: Use fallthrough pseudo-keyword
pinctrl: qcom: spmi-gpio: Use fallthrough pseudo-keyword
pinctrl: baytrail: Use fallthrough pseudo-keyword
...
Diffstat (limited to 'drivers/pinctrl/pinctrl-rza1.c')
-rw-r--r-- | drivers/pinctrl/pinctrl-rza1.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/pinctrl/pinctrl-rza1.c b/drivers/pinctrl/pinctrl-rza1.c index 38a14bbced5f..511f232ab7bc 100644 --- a/drivers/pinctrl/pinctrl-rza1.c +++ b/drivers/pinctrl/pinctrl-rza1.c @@ -75,7 +75,7 @@ * RZ/A1 pinmux flags */ -/** +/* * rza1_bidir_pin - describe a single pin that needs bidir flag applied. */ struct rza1_bidir_pin { @@ -83,7 +83,7 @@ struct rza1_bidir_pin { u8 func: 4; }; -/** +/* * rza1_bidir_entry - describe a list of pins that needs bidir flag applied. * Each struct rza1_bidir_entry describes a port. */ @@ -92,7 +92,7 @@ struct rza1_bidir_entry { const struct rza1_bidir_pin *pins; }; -/** +/* * rza1_swio_pin - describe a single pin that needs swio flag applied. */ struct rza1_swio_pin { @@ -102,7 +102,7 @@ struct rza1_swio_pin { u16 input: 1; }; -/** +/* * rza1_swio_entry - describe a list of pins that needs swio flag applied */ struct rza1_swio_entry { @@ -110,7 +110,7 @@ struct rza1_swio_entry { const struct rza1_swio_pin *pins; }; -/** +/* * rza1_pinmux_conf - group together bidir and swio pinmux flag tables */ struct rza1_pinmux_conf { @@ -431,7 +431,7 @@ static const struct rza1_pinmux_conf rza1l_pmx_conf = { * RZ/A1 types */ /** - * rza1_mux_conf - describes a pin multiplexing operation + * struct rza1_mux_conf - describes a pin multiplexing operation * * @id: the pin identifier from 0 to RZA1_NPINS * @port: the port where pin sits on @@ -450,7 +450,7 @@ struct rza1_mux_conf { }; /** - * rza1_port - describes a pin port + * struct rza1_port - describes a pin port * * This is mostly useful to lock register writes per-bank and not globally. * @@ -467,12 +467,12 @@ struct rza1_port { }; /** - * rza1_pinctrl - RZ pincontroller device + * struct rza1_pinctrl - RZ pincontroller device * * @dev: parent device structure * @mutex: protect [pinctrl|pinmux]_generic functions * @base: logical address base - * @nports: number of pin controller ports + * @nport: number of pin controller ports * @ports: pin controller banks * @pins: pin array for pinctrl core * @desc: pincontroller desc for pinctrl core @@ -536,7 +536,7 @@ static inline int rza1_pinmux_get_swio(unsigned int port, return -ENOENT; } -/** +/* * rza1_pinmux_get_flags() - return pinmux flags associated to a pin */ static unsigned int rza1_pinmux_get_flags(unsigned int port, unsigned int pin, @@ -566,7 +566,7 @@ static unsigned int rza1_pinmux_get_flags(unsigned int port, unsigned int pin, * RZ/A1 SoC operations */ -/** +/* * rza1_set_bit() - un-locked set/clear a single bit in pin configuration * registers */ @@ -664,7 +664,7 @@ static inline int rza1_pin_get(struct rza1_port *port, unsigned int pin) /** * rza1_pin_mux_single() - configure pin multiplexing on a single pin * - * @pinctrl: RZ/A1 pin controller device + * @rza1_pctl: RZ/A1 pin controller device * @mux_conf: pin multiplexing descriptor */ static int rza1_pin_mux_single(struct rza1_pinctrl *rza1_pctl, |