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| author | Michael Walle <michael@walle.cc> | 2022-04-20 21:19:25 +0200 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2022-04-29 00:38:47 +0200 |
| commit | 9c1082fd1b1b8fd0f990ef917ddeff977fd320ab (patch) | |
| tree | 88ea9f51aa90c3609132997d07096dc8fa36443f /drivers/pinctrl/pinctrl-rockchip.h | |
| parent | 69ab1e16d3823c05892371cd2c89e7852ac87067 (diff) | |
| download | linux-9c1082fd1b1b8fd0f990ef917ddeff977fd320ab.tar.bz2 | |
dt-bindings: pinctrl: ocelot: add reset property
On the LAN966x SoC the GPIO controller will be resetted together with
the SGPIO and the switch core. Add a phandle to register the shared
reset line.
Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220420191926.3411830-2-michael@walle.cc
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/pinctrl-rockchip.h')
0 files changed, 0 insertions, 0 deletions