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author | Linus Torvalds <torvalds@linux-foundation.org> | 2015-06-24 19:21:02 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2015-06-24 19:21:02 -0700 |
commit | 93a4b1b9465d92e8be031b57166afa3d5611e142 (patch) | |
tree | 0ac95e35f24a754e01bdc40c56d71068eed49e4c /drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c | |
parent | d59b92f93df2d545d87d2341eb0705cc926ea22a (diff) | |
parent | daecdc66968f122fe53038ded8cb7abe93e0aa8c (diff) | |
download | linux-93a4b1b9465d92e8be031b57166afa3d5611e142.tar.bz2 |
Merge tag 'pinctrl-v4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"Here is the bulk of pin control changes for the v4.2 series: Quite a
lot of new SoC subdrivers and two new main drivers this time, apart
from that business as usual.
Details:
Core functionality:
- Enable exclusive pin ownership: it is possible to flag a pin
controller so that GPIO and other functions cannot use a single pin
simultaneously.
New drivers:
- NXP LPC18xx System Control Unit pin controller
- Imagination Pistachio SoC pin controller
New subdrivers:
- Freescale i.MX7d SoC
- Intel Sunrisepoint-H PCH
- Renesas PFC R8A7793
- Renesas PFC R8A7794
- Mediatek MT6397, MT8127
- SiRF Atlas 7
- Allwinner A33
- Qualcomm MSM8660
- Marvell Armada 395
- Rockchip RK3368
Cleanups:
- A big cleanup of the Marvell MVEBU driver rectifying it to
correspond to reality
- Drop platform device probing from the SH PFC driver, we are now a
DT only shop for SuperH
- Drop obsolte multi-platform check for SH PFC
- Various janitorial: constification, grammar etc
Improvements:
- The AT91 GPIO portions now supports the set_multiple() feature
- Split out SPI pins on the Xilinx Zynq
- Support DTs without specific function nodes in the i.MX driver"
* tag 'pinctrl-v4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (99 commits)
pinctrl: rockchip: add support for the rk3368
pinctrl: rockchip: generalize perpin driver-strength setting
pinctrl: sh-pfc: r8a7794: add SDHI pin groups
pinctrl: sh-pfc: r8a7794: add MMCIF pin groups
pinctrl: sh-pfc: add R8A7794 PFC support
pinctrl: make pinctrl_register() return proper error code
pinctrl: mvebu: armada-39x: add support for Armada 395 variant
pinctrl: mvebu: armada-39x: add missing SATA functions
pinctrl: mvebu: armada-39x: add missing PCIe functions
pinctrl: mvebu: armada-38x: add ptp functions
pinctrl: mvebu: armada-38x: add ua1 functions
pinctrl: mvebu: armada-38x: add nand functions
pinctrl: mvebu: armada-38x: add sata functions
pinctrl: mvebu: armada-xp: add dram functions
pinctrl: mvebu: armada-xp: add nand rb function
pinctrl: mvebu: armada-xp: add spi1 function
pinctrl: mvebu: armada-39x: normalize ref clock naming
pinctrl: mvebu: armada-xp: rename spi to spi0
pinctrl: mvebu: armada-370: align spi1 clock pin naming
pinctrl: mvebu: armada-370: align VDD cpu-pd pin naming with datasheet
...
Diffstat (limited to 'drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c')
-rw-r--r-- | drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c index e406e3d8c1c7..7d9482bf8252 100644 --- a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c @@ -38,7 +38,7 @@ #define CYGNUS_GPIO_DATA_IN_OFFSET 0x00 #define CYGNUS_GPIO_DATA_OUT_OFFSET 0x04 #define CYGNUS_GPIO_OUT_EN_OFFSET 0x08 -#define CYGNUS_GPIO_IN_TYPE_OFFSET 0x0c +#define CYGNUS_GPIO_INT_TYPE_OFFSET 0x0c #define CYGNUS_GPIO_INT_DE_OFFSET 0x10 #define CYGNUS_GPIO_INT_EDGE_OFFSET 0x14 #define CYGNUS_GPIO_INT_MSK_OFFSET 0x18 @@ -264,7 +264,7 @@ static int cygnus_gpio_irq_set_type(struct irq_data *d, unsigned int type) } spin_lock_irqsave(&chip->lock, flags); - cygnus_set_bit(chip, CYGNUS_GPIO_IN_TYPE_OFFSET, gpio, + cygnus_set_bit(chip, CYGNUS_GPIO_INT_TYPE_OFFSET, gpio, level_triggered); cygnus_set_bit(chip, CYGNUS_GPIO_INT_DE_OFFSET, gpio, dual_edge); cygnus_set_bit(chip, CYGNUS_GPIO_INT_EDGE_OFFSET, gpio, @@ -750,9 +750,9 @@ static int cygnus_gpio_register_pinconf(struct cygnus_gpio *chip) pctldesc->confops = &cygnus_pconf_ops; chip->pctl = pinctrl_register(pctldesc, chip->dev, chip); - if (!chip->pctl) { + if (IS_ERR(chip->pctl)) { dev_err(chip->dev, "unable to register pinctrl device\n"); - return -EINVAL; + return PTR_ERR(chip->pctl); } return 0; |