Merge tag 'pinctrl-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "Core changes:

   - NONE whatsoever, we don't even touch the core files this time
     around.

  New drivers:

   - New driver for the Toshiba Visconti SoC.

   - New subdriver for the Qualcomm MSM8226 SoC.

   - New subdriver for the Actions Semiconductor S500 SoC.

   - New subdriver for the Mediatek MT8192 SoC.

   - New subdriver for the Microchip SAMA7G5 SoC.

  Driver enhancements:

   - Intel Cherryview and Baytrail cleanups and refactorings.

   - Enhanced support for the Renesas R8A7790, more pins and groups.

   - Some optimizations for the MCP23S08 MCP23x17 variant.

   - Some cleanups around the Actions Semiconductor subdrivers.

   - A bunch of cleanups around the SH-PFC and Emma Mobile drivers.

   - The "SH-PFC" (literally SuperH pin function controller, I think)
     subdirectory is now renamed to the more neutral "renesas", as these
     are not very much centered around SuperH anymore.

   - Non-critical fixes for the Aspeed driver.

   - Non-critical fixes for the Ingenic (MIPS!) driver.

   - Fix a bunch of missing pins on the AMD pinctrl driver"

* tag 'pinctrl-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (78 commits)
  pinctrl: amd: Add missing pins to the pin group list
  dt-bindings: pinctrl: sunxi: Allow pinctrl with more interrupt banks
  pinctrl: visconti: PINCTRL_TMPV7700 should depend on ARCH_VISCONTI
  pinctrl: mediatek: Free eint data on failure
  pinctrl: single: fix debug output when #pinctrl-cells = 2
  pinctrl: single: fix pinctrl_spec.args_count bounds check
  pinctrl: sunrisepoint: Modify COMMUNITY macros to be consistent
  pinctrl: cannonlake: Modify COMMUNITY macros to be consistent
  pinctrl: tigerlake: Fix register offsets for TGL-H variant
  pinctrl: Document pinctrl-single,pins when #pinctrl-cells = 2
  pinctrl: mediatek: use devm_platform_ioremap_resource_byname()
  pinctrl: nuvoton: npcm7xx: Constify static ops structs
  pinctrl: mediatek: mt7622: add antsel pins/groups
  pinctrl: ocelot: simplify the return expression of ocelot_gpiochip_register()
  pinctrl: at91-pio4: add support for sama7g5 SoC
  dt-bindings: pinctrl: at91-pio4: add microchip,sama7g5
  pinctrl: spear: simplify the return expression of tvc_connect()
  pinctrl: spear: simplify the return expression of spear310_pinctrl_probe
  pinctrl: sprd: use module_platform_driver to simplify the code
  pinctrl: Ingenic: Add I2S pins support for Ingenic SoCs.
  ...

2 files changed, 21 insertions, 4 deletions

diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
index 7efe6dbe4398..34803a6c7664 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
@@ -19,6 +19,7 @@
 
 #define SCU400		0x400 /* Multi-function Pin Control #1  */
 #define SCU404		0x404 /* Multi-function Pin Control #2  */
+#define SCU40C		0x40C /* Multi-function Pin Control #3  */
 #define SCU410		0x410 /* Multi-function Pin Control #4  */
 #define SCU414		0x414 /* Multi-function Pin Control #5  */
 #define SCU418		0x418 /* Multi-function Pin Control #6  */
@@ -2591,6 +2592,22 @@ static struct aspeed_pin_config aspeed_g6_configs[] = {
 	/* MAC4 */
 	{ PIN_CONFIG_POWER_SOURCE,   { F24, B24 }, SCU458, BIT_MASK(5)},
 	{ PIN_CONFIG_DRIVE_STRENGTH, { F24, B24 }, SCU458, GENMASK(3, 2)},
+
+	/* GPIO18E */
+	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y1, Y4, SCU40C, 4),
+	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE,   Y1, Y4, SCU40C, 4),
+	/* GPIO18D */
+	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, AB4, AC5, SCU40C, 3),
+	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE,   AB4, AC5, SCU40C, 3),
+	/* GPIO18C */
+	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E4, E1, SCU40C, 2),
+	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE,   E4, E1, SCU40C, 2),
+	/* GPIO18B */
+	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B2, D3, SCU40C, 1),
+	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE,   B2, D3, SCU40C, 1),
+	/* GPIO18A */
+	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C6, A2, SCU40C, 0),
+	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE,   C6, A2, SCU40C, 0),
 };
 
 /**
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c
index 53f3f8aec695..6a94eaecf638 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c
@@ -534,14 +534,14 @@ int aspeed_pin_config_set(struct pinctrl_dev *pctldev, unsigned int offset,
 		val = pmap->val << __ffs(pconf->mask);
 
 		rc = regmap_update_bits(pdata->scu, pconf->reg,
-					pmap->mask, val);
+					pconf->mask, val);
 
 		if (rc < 0)
 			return rc;
 
-		pr_debug("%s: Set SCU%02X[%lu]=%d for param %d(=%d) on pin %d\n",
-				__func__, pconf->reg, __ffs(pconf->mask),
-				pmap->val, param, arg, offset);
+		pr_debug("%s: Set SCU%02X[0x%08X]=0x%X for param %d(=%d) on pin %d\n",
+				__func__, pconf->reg, pconf->mask,
+				val, param, arg, offset);
 	}
 
 	return 0;