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authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>2021-12-30 14:02:16 +0100
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2021-12-30 14:02:16 +0100
commite75a58db41df67e6282104aaae073bc8b43b8dc8 (patch)
tree7663fad1da606196cc1fa985e6893c67a1bac14f /drivers/phy/ti
parent1563fca2346c31da30324cefe2e59a2afe0f61fa (diff)
parent09d976b3e8e257ff44405b6506bbaae6be1a6b3c (diff)
downloadlinux-e75a58db41df67e6282104aaae073bc8b43b8dc8.tar.bz2
Merge tag 'phy-for-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into char-misc-next
Vinod writes: phy-for-5.17 - New support: - Qualcomm eDP PHY driver - Qualcomm SM8450 UFS, USB2, USB3, PCIe0 and PCIe1 phy support - Lan966x ethernet serdes PHY driver - Support for uniphier NXI & Pro4 SoC - Qualcomm SM6350 USB2 support - Amlogic Meson8 HDMI TX PHY driver - Rockchip rk3568 usb2 support - Intel Thunder Bay eMMC PHY driver - Freescale IMX8 PCIe phy driver - Updates: - Cadence Sierra driver updates for multilink configurations - Bcm usb2 updates for Phy reg space * tag 'phy-for-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (72 commits) phy: cadence: Sierra: Add support for derived reference clock output dt-bindings: phy: cadence-sierra: Add clock ID for derived reference clock phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration phy: cadence: Sierra: Add support for PHY multilink configurations phy: cadence: Sierra: Fix to get correct parent for mux clocks phy: cadence: Sierra: Update single link PCIe register configuration phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation phy: cadence: Sierra: Check cmn_ready assertion during PHY power on phy: cadence: Sierra: Add PHY PCS common register configurations phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation phy: cadence: Sierra: Add support to get SSC type from device tree dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode dt-bindings: phy: cadence-torrent: Rename SSC macros to use generic names phy: cadence: Sierra: Prepare driver to add support for multilink configurations phy: cadence: Sierra: Use of_device_get_match_data() to get driver data phy: mediatek: Fix missing check in mtk_mipi_tx_probe phy: uniphier-usb3ss: fix unintended writing zeros to PHY register phy: phy-mtk-tphy: use new io helpers to access register phy: phy-mtk-xsphy: use new io helpers to access register phy: mediatek: add helpers to update bits of registers ...
Diffstat (limited to 'drivers/phy/ti')
-rw-r--r--drivers/phy/ti/phy-omap-control.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/phy/ti/phy-omap-control.c b/drivers/phy/ti/phy-omap-control.c
index 47482f106fab..76c5595f0859 100644
--- a/drivers/phy/ti/phy-omap-control.c
+++ b/drivers/phy/ti/phy-omap-control.c
@@ -26,7 +26,7 @@ void omap_control_pcie_pcs(struct device *dev, u8 delay)
u32 val;
struct omap_control_phy *control_phy;
- if (IS_ERR(dev) || !dev) {
+ if (IS_ERR_OR_NULL(dev)) {
pr_err("%s: invalid device\n", __func__);
return;
}
@@ -61,7 +61,7 @@ void omap_control_phy_power(struct device *dev, int on)
unsigned long rate;
struct omap_control_phy *control_phy;
- if (IS_ERR(dev) || !dev) {
+ if (IS_ERR_OR_NULL(dev)) {
pr_err("%s: invalid device\n", __func__);
return;
}
@@ -202,7 +202,7 @@ void omap_control_usb_set_mode(struct device *dev,
{
struct omap_control_phy *ctrl_phy;
- if (IS_ERR(dev) || !dev)
+ if (IS_ERR_OR_NULL(dev))
return;
ctrl_phy = dev_get_drvdata(dev);