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| author | Andre Przywara <andre.przywara@arm.com> | 2022-02-02 19:35:56 -0600 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2022-02-25 13:53:21 +0530 |
| commit | 1743dea7f06b939f67ba258bab993fa5ff6e43fb (patch) | |
| tree | 1850c239b8fae97fe20f9b3ab975aef59e4b5dde /drivers/phy/ti/phy-gmii-sel.c | |
| parent | 5df4afa1e4388744f20177bdfbaf4fcafc31017b (diff) | |
| download | linux-1743dea7f06b939f67ba258bab993fa5ff6e43fb.tar.bz2 | |
phy: sun4i-usb: Rework HCI PHY (aka "pmu_unk1") handling
As Icenowy pointed out, newer manuals (starting with H6) actually
document the register block at offset 0x800 as "HCI controller and PHY
interface", also describe the bits in our "PMU_UNK1" register.
Let's put proper names to those "unknown" variables and symbols.
While we are at it, generalise the existing code by allowing a bitmap
of bits to clear and set, to cover newer SoCs: The A100 and H616 use a
different bit for the SIDDQ control.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20220203013558.11490-3-samuel@sholland.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/phy/ti/phy-gmii-sel.c')
0 files changed, 0 insertions, 0 deletions