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| author | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2022-11-02 13:48:35 +0530 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2022-11-10 12:45:46 +0530 |
| commit | 883aebf6e1ea88145d64dcf940dbcb5181313338 (patch) | |
| tree | bcfa8821ebd18443e1c1956b53df1e57b5896d15 /drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5_20.h | |
| parent | 9ddcd920f8edfe65c3670fbd0b49db00e1e562fe (diff) | |
| download | linux-883aebf6e1ea88145d64dcf940dbcb5181313338.tar.bz2 | |
phy: qcom-qmp-pcie: Fix sm8450_qmp_gen4x2_pcie_pcs_tbl[] register names
sm8450_qmp_gen4x2_pcie_pcs_tbl[] contains the init sequence for PCS
registers of QMP PHY v5.20. So use the v5.20 specific register names.
Only major change is the rename of PCS_EQ_CONFIG{2/3} registers to
PCS_EQ_CONFIG{4/5}.
Fixes: 2c91bf6bf290 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20221102081835.41892-2-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5_20.h')
| -rw-r--r-- | drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5_20.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5_20.h new file mode 100644 index 000000000000..9a5a20daf62c --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5_20.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2022, Linaro Ltd. + */ + +#ifndef QCOM_PHY_QMP_PCS_V5_20_H_ +#define QCOM_PHY_QMP_PCS_V5_20_H_ + +#define QPHY_V5_20_PCS_G3S2_PRE_GAIN 0x170 +#define QPHY_V5_20_PCS_RX_SIGDET_LVL 0x188 +#define QPHY_V5_20_PCS_EQ_CONFIG4 0x1e0 +#define QPHY_V5_20_PCS_EQ_CONFIG5 0x1e4 + +#endif |