diff options
| author | Hao Fang <fanghao11@huawei.com> | 2021-05-22 18:23:57 +0800 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2021-06-01 14:18:47 +0100 |
| commit | 2db5223731b79cf5c617dc391ceb21dd5cb93237 (patch) | |
| tree | afc5f1c111bbd6f463b9ca8a2403c4f712e5dbfc /drivers/perf | |
| parent | a5740e955540181f4ab8f076cc9795c6bbe4d730 (diff) | |
| download | linux-2db5223731b79cf5c617dc391ceb21dd5cb93237.tar.bz2 | |
drivers/perf: hisi: use the correct HiSilicon copyright
s/Hisilicon/HiSilicon/.
It should use capital S, according to the official website
https://www.hisilicon.com/en.
Signed-off-by: Hao Fang <fanghao11@huawei.com>
Link: https://lore.kernel.org/r/1621679037-15323-1-git-send-email-fanghao11@huawei.com
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'drivers/perf')
| -rw-r--r-- | drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c | 2 | ||||
| -rw-r--r-- | drivers/perf/hisilicon/hisi_uncore_hha_pmu.c | 2 | ||||
| -rw-r--r-- | drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c | 2 | ||||
| -rw-r--r-- | drivers/perf/hisilicon/hisi_uncore_pmu.c | 2 | ||||
| -rw-r--r-- | drivers/perf/hisilicon/hisi_uncore_pmu.h | 2 | ||||
| -rw-r--r-- | drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c | 2 |
6 files changed, 6 insertions, 6 deletions
diff --git a/drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c b/drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c index 0c7777bf1542..62299ab5a9be 100644 --- a/drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c @@ -2,7 +2,7 @@ /* * HiSilicon SoC DDRC uncore Hardware event counters support * - * Copyright (C) 2017 Hisilicon Limited + * Copyright (C) 2017 HiSilicon Limited * Author: Shaokun Zhang <zhangshaokun@hisilicon.com> * Anurup M <anurup.m@huawei.com> * diff --git a/drivers/perf/hisilicon/hisi_uncore_hha_pmu.c b/drivers/perf/hisilicon/hisi_uncore_hha_pmu.c index 12eb41ab1b8a..12b2c5e6d488 100644 --- a/drivers/perf/hisilicon/hisi_uncore_hha_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_hha_pmu.c @@ -2,7 +2,7 @@ /* * HiSilicon SoC HHA uncore Hardware event counters support * - * Copyright (C) 2017 Hisilicon Limited + * Copyright (C) 2017 HiSilicon Limited * Author: Shaokun Zhang <zhangshaokun@hisilicon.com> * Anurup M <anurup.m@huawei.com> * diff --git a/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c b/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c index 773f69538090..560ab964c8b5 100644 --- a/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_l3c_pmu.c @@ -2,7 +2,7 @@ /* * HiSilicon SoC L3C uncore Hardware event counters support * - * Copyright (C) 2017 Hisilicon Limited + * Copyright (C) 2017 HiSilicon Limited * Author: Anurup M <anurup.m@huawei.com> * Shaokun Zhang <zhangshaokun@hisilicon.com> * diff --git a/drivers/perf/hisilicon/hisi_uncore_pmu.c b/drivers/perf/hisilicon/hisi_uncore_pmu.c index 5842593632e4..a738aeab5c04 100644 --- a/drivers/perf/hisilicon/hisi_uncore_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_pmu.c @@ -2,7 +2,7 @@ /* * HiSilicon SoC Hardware event counters support * - * Copyright (C) 2017 Hisilicon Limited + * Copyright (C) 2017 HiSilicon Limited * Author: Anurup M <anurup.m@huawei.com> * Shaokun Zhang <zhangshaokun@hisilicon.com> * diff --git a/drivers/perf/hisilicon/hisi_uncore_pmu.h b/drivers/perf/hisilicon/hisi_uncore_pmu.h index ea9d89bbc1ea..7f5841d6f592 100644 --- a/drivers/perf/hisilicon/hisi_uncore_pmu.h +++ b/drivers/perf/hisilicon/hisi_uncore_pmu.h @@ -2,7 +2,7 @@ /* * HiSilicon SoC Hardware event counters support * - * Copyright (C) 2017 Hisilicon Limited + * Copyright (C) 2017 HiSilicon Limited * Author: Anurup M <anurup.m@huawei.com> * Shaokun Zhang <zhangshaokun@hisilicon.com> * diff --git a/drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c b/drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c index 835ec3e2178f..08e028d9a406 100644 --- a/drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_sllc_pmu.c @@ -2,7 +2,7 @@ /* * HiSilicon SLLC uncore Hardware event counters support * - * Copyright (C) 2020 Hisilicon Limited + * Copyright (C) 2020 HiSilicon Limited * Author: Shaokun Zhang <zhangshaokun@hisilicon.com> * * This code is based on the uncore PMUs like arm-cci and arm-ccn. |