diff options
| author | Dave Airlie <airlied@redhat.com> | 2020-03-11 07:27:21 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2020-03-11 07:27:21 +1000 |
| commit | d3bd37f587b4438d47751d0f1d5aaae3d39bd416 (patch) | |
| tree | 9414a8fd1ca74c47fe1a3966e0a22469ac0b73a3 /drivers/perf/fsl_imx8_ddr_perf.c | |
| parent | 60347451ddb0646c1a9cc5b9581e5bcf648ad1aa (diff) | |
| parent | 2c523b344dfa65a3738e7039832044aa133c75fb (diff) | |
| download | linux-d3bd37f587b4438d47751d0f1d5aaae3d39bd416.tar.bz2 | |
Merge v5.6-rc5 into drm-next
Requested my mripard for some misc patches that need this as a base.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/perf/fsl_imx8_ddr_perf.c')
| -rw-r--r-- | drivers/perf/fsl_imx8_ddr_perf.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c index 95dca2cb5265..90884d14f95f 100644 --- a/drivers/perf/fsl_imx8_ddr_perf.c +++ b/drivers/perf/fsl_imx8_ddr_perf.c @@ -388,9 +388,10 @@ static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config, if (enable) { /* - * must disable first, then enable again - * otherwise, cycle counter will not work - * if previous state is enabled. + * cycle counter is special which should firstly write 0 then + * write 1 into CLEAR bit to clear it. Other counters only + * need write 0 into CLEAR bit and it turns out to be 1 by + * hardware. Below enable flow is harmless for all counters. */ writel(0, pmu->base + reg); val = CNTL_EN | CNTL_CLEAR; @@ -398,7 +399,8 @@ static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config, writel(val, pmu->base + reg); } else { /* Disable counter */ - writel(0, pmu->base + reg); + val = readl_relaxed(pmu->base + reg) & CNTL_EN_MASK; + writel(val, pmu->base + reg); } } |