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authorBrian Norris <briannorris@chromium.org>2016-12-07 15:06:00 -0600
committerBjorn Helgaas <bhelgaas@google.com>2016-12-07 15:06:00 -0600
commita45e2611b9bbd81288d97d02ce7e74a60a698d43 (patch)
tree89a8602cb35cf0da9ea7e7590bf5485ec637bae7 /drivers/pci
parent77bc68cf17973ee81e1cbc21d634c99aa8dca014 (diff)
downloadlinux-a45e2611b9bbd81288d97d02ce7e74a60a698d43.tar.bz2
PCI: rockchip: Correct the use of FTS mask
We're trying to mask out bits[23:8] while retaining [32:24, 7:0], but we're doing the inverse. That doesn't have too much effect, since we're setting all the [23:8] bits to 1, and the other bits are only relevant for modes we're currently not using. But we should get this right. Fixes: ca1989084054 ("PCI: rockchip: Fix wrong transmitted FTS count") Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/host/pcie-rockchip.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 17df584742ff..5ff2f698e03a 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -573,7 +573,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
/* Fix the transmitted FTS count desired to exit from L0s. */
status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_PLC1);
- status = (status & PCIE_CORE_CTRL_PLC1_FTS_MASK) |
+ status = (status & ~PCIE_CORE_CTRL_PLC1_FTS_MASK) |
(PCIE_CORE_CTRL_PLC1_FTS_CNT << PCIE_CORE_CTRL_PLC1_FTS_SHIFT);
rockchip_pcie_write(rockchip, status, PCIE_CORE_CTRL_PLC1);