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authorBjorn Helgaas <bhelgaas@google.com>2018-04-04 13:28:57 -0500
committerBjorn Helgaas <helgaas@kernel.org>2018-04-04 13:28:57 -0500
commit7432acf315254aae540609d2370543b5488a317a (patch)
tree471a0e0b8cd09f3f2262f95cf3b930b75704982c /drivers/pci
parentd2f48c5d7fd791104f3227d8e6b55fca892eb2ba (diff)
parent745029187a5465972fa2daf0fa43f1d2edb48de9 (diff)
downloadlinux-7432acf315254aae540609d2370543b5488a317a.tar.bz2
Merge branch 'lorenzo/pci/xilinx'
* lorenzo/pci/xilinx: PCI: pcie-xilinx-nwl: Fix mask value to disable MSIs
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/host/pcie-xilinx-nwl.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/pci/host/pcie-xilinx-nwl.c b/drivers/pci/host/pcie-xilinx-nwl.c
index 0acaf483d031..4839ae578711 100644
--- a/drivers/pci/host/pcie-xilinx-nwl.c
+++ b/drivers/pci/host/pcie-xilinx-nwl.c
@@ -630,7 +630,7 @@ static int nwl_pcie_enable_msi(struct nwl_pcie *pcie)
* For high range MSI interrupts: disable, clear any pending,
* and enable
*/
- nwl_bridge_writel(pcie, (u32)~MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);
+ nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI);
nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) &
MSGF_MSI_SR_HI_MASK, MSGF_MSI_STATUS_HI);
@@ -641,7 +641,7 @@ static int nwl_pcie_enable_msi(struct nwl_pcie *pcie)
* For low range MSI interrupts: disable, clear any pending,
* and enable
*/
- nwl_bridge_writel(pcie, (u32)~MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);
+ nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO);
nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) &
MSGF_MSI_SR_LO_MASK, MSGF_MSI_STATUS_LO);