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authorBjorn Helgaas <bhelgaas@google.com>2020-04-02 14:26:27 -0500
committerBjorn Helgaas <bhelgaas@google.com>2020-04-02 14:26:27 -0500
commitdd956a123699b5df6cc376ef6575e80ff018119a (patch)
tree5f5e47075ab1ba67ace0f945b8127037b8921c3d /drivers/pci/pcie/aspm.c
parentbb6d3fb354c5ee8d6bde2d576eb7220ea09862b9 (diff)
parent3b364c659bd38fa07b4f035eeb3c15469a39b0d6 (diff)
downloadlinux-dd956a123699b5df6cc376ef6575e80ff018119a.tar.bz2
Merge branch 'pci/aspm'
- Clear the correct bits when enabling ASPM L1 substates (Yicong Yang) - Reduce severity of ASPM common clock config message (Chris Packham) * pci/aspm: PCI/ASPM: Reduce severity of common clock config message PCI/ASPM: Clear the correct bits when enabling L1 substates
Diffstat (limited to 'drivers/pci/pcie/aspm.c')
-rw-r--r--drivers/pci/pcie/aspm.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index 0dcd44308228..2378ed692534 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -273,7 +273,7 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
}
if (consistent)
return;
- pci_warn(parent, "ASPM: current common clock configuration is broken, reconfiguring\n");
+ pci_info(parent, "ASPM: current common clock configuration is inconsistent, reconfiguring\n");
}
/* Configure downstream component, all functions */
@@ -747,9 +747,9 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
/* Enable what we need to enable */
pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
- PCI_L1SS_CAP_L1_PM_SS, val);
+ PCI_L1SS_CTL1_L1SS_MASK, val);
pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
- PCI_L1SS_CAP_L1_PM_SS, val);
+ PCI_L1SS_CTL1_L1SS_MASK, val);
}
static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)