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| author | Sinan Kaya <okaya@codeaurora.org> | 2018-02-27 14:14:10 -0600 |
|---|---|---|
| committer | Bjorn Helgaas <helgaas@kernel.org> | 2018-03-05 08:10:14 -0600 |
| commit | abbcf0e2a99d55433b2ee44794e6f875fc36aae2 (patch) | |
| tree | d6ae14b8e851c3ad627cebdfc5275f63b992a17e /drivers/pci/pci.c | |
| parent | a2758b6b8fdba5f1045f571fdb39d9bdb8ba0813 (diff) | |
| download | linux-abbcf0e2a99d55433b2ee44794e6f875fc36aae2.tar.bz2 | |
PCI: Wait for device to become ready after a power management reset
PCIe r4.0, sec 2.3.1, Request Handling Rules, indicates that a device can
return CRS Completion Status following a D3hot to D0 transition. Wait
until the device becomes ready in that situation.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Diffstat (limited to 'drivers/pci/pci.c')
| -rw-r--r-- | drivers/pci/pci.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 9493b97436c3..a3042e475901 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4188,7 +4188,7 @@ static int pci_pm_reset(struct pci_dev *dev, int probe) pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); pci_dev_d3_sleep(dev); - return 0; + return pci_dev_wait(dev, "PM D3->D0", PCIE_RESET_READY_POLL_MS); } void pci_reset_secondary_bus(struct pci_dev *dev) |