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| author | Sinan Kaya <okaya@codeaurora.org> | 2018-02-27 14:14:12 -0600 |
|---|---|---|
| committer | Bjorn Helgaas <helgaas@kernel.org> | 2018-03-05 08:10:14 -0600 |
| commit | 6b2f1351af567110cec80d7c067314c633a14f50 (patch) | |
| tree | 333c32d43c22310b0a758b410a7699c756e3d8be /drivers/pci/pci.c | |
| parent | 01fd61c0b9bd85ab41fb60fbd781d44882ee6887 (diff) | |
| download | linux-6b2f1351af567110cec80d7c067314c633a14f50.tar.bz2 | |
PCI: Wait for device to become ready after secondary bus reset
Setting Secondary Bus Reset of a downstream port sends a hot reset. PCIe
r4.0, sec 2.3.1, Request Handling Rules, indicates that a device can return
CRS Completion Status following such a reset. Wait until the device
becomes ready in that situation.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Diffstat (limited to 'drivers/pci/pci.c')
| -rw-r--r-- | drivers/pci/pci.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index dde40506ffe5..0b8e8ee84bbc 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4233,7 +4233,7 @@ int pci_reset_bridge_secondary_bus(struct pci_dev *dev) { pcibios_reset_secondary_bus(dev); - return 0; + return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS); } EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus); |