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| author | Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> | 2022-07-05 16:26:45 +0530 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2022-07-22 14:12:00 -0500 |
| commit | 49f40703ca91c8428dd35e7331ae6c098e61b100 (patch) | |
| tree | 3fe5e407cc19e489aa3b01dd8483f6ef771598ee /drivers/pci/controller/dwc/pcie-uniphier.c | |
| parent | f2906aa863381afb0015a9eb7fefad885d4e5a56 (diff) | |
| download | linux-49f40703ca91c8428dd35e7331ae6c098e61b100.tar.bz2 | |
dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
Xilinx Versal Premium series has CPM5 block which supports Root Port
functionality at Gen5 speed.
Add support for YAML schemas documentation for Versal CPM5 Root Port driver.
Link: https://lore.kernel.org/r/20220705105646.16980-2-bharat.kumar.gogada@xilinx.com
Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'drivers/pci/controller/dwc/pcie-uniphier.c')
0 files changed, 0 insertions, 0 deletions