diff options
| author | Bjorn Helgaas <bhelgaas@google.com> | 2021-02-24 14:59:21 -0600 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2021-02-24 14:59:21 -0600 |
| commit | 59189d06e06cfc57d215a8ad1d92d42b2730e380 (patch) | |
| tree | 21c8d16b64a6985145fad6586835cdf9876a8a24 /drivers/pci/controller/cadence/pcie-cadence.h | |
| parent | 93aed5215dcada4deb42be100695c2f8935623a9 (diff) | |
| parent | 4740b969aaf58adeca6829947a3ad8da423976cf (diff) | |
| download | linux-59189d06e06cfc57d215a8ad1d92d42b2730e380.tar.bz2 | |
Merge branch 'remotes/lorenzo/pci/cadence'
- Retrain Link to work around Gen2 training defect (Nadeem Athani)
* remotes/lorenzo/pci/cadence:
PCI: cadence: Retrain Link to work around Gen2 training defect
Diffstat (limited to 'drivers/pci/controller/cadence/pcie-cadence.h')
| -rw-r--r-- | drivers/pci/controller/cadence/pcie-cadence.h | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index 30eba6cafe2c..254d2570f8c9 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -119,7 +119,7 @@ * Root Port Registers (PCI configuration space for the root port function) */ #define CDNS_PCIE_RP_BASE 0x00200000 - +#define CDNS_PCIE_RP_CAP_OFFSET 0xc0 /* * Address Translation Registers @@ -291,6 +291,7 @@ struct cdns_pcie { * @device_id: PCI device ID * @avail_ib_bar: Satus of RP_BAR0, RP_BAR1 and RP_NO_BAR if it's free or * available + * @quirk_retrain_flag: Retrain link as quirk for PCIe Gen2 */ struct cdns_pcie_rc { struct cdns_pcie pcie; @@ -299,6 +300,7 @@ struct cdns_pcie_rc { u32 vendor_id; u32 device_id; bool avail_ib_bar[CDNS_PCIE_RP_MAX_IB]; + bool quirk_retrain_flag; }; /** @@ -414,6 +416,13 @@ static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie, cdns_pcie_write_sz(addr, 0x2, value); } +static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg) +{ + void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; + + return cdns_pcie_read_sz(addr, 0x2); +} + /* Endpoint Function register access */ static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn, u32 reg, u8 value) |