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| author | Parshuram Thombare <pthombar@cadence.com> | 2021-10-25 05:31:15 -0700 |
|---|---|---|
| committer | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2022-05-12 22:19:40 +0100 |
| commit | 95b00f68209e2bc9f2ee9126afcebab451e0e9d8 (patch) | |
| tree | 1d97ec467b42360d5cf93928a83c6c8ccc5850ec /drivers/pci/controller/cadence/pcie-cadence.c | |
| parent | a1f67bc131c3935f325513cd153249fdbc22ac5b (diff) | |
| download | linux-95b00f68209e2bc9f2ee9126afcebab451e0e9d8.tar.bz2 | |
PCI: cadence: Clear FLR in device capabilities register
Clear FLR (Function Level Reset) from device capabilities
registers for all physical functions.
During FLR, the Margining Lane Status and Margining Lane Control
registers should not be reset, as per PCIe specification.
However, the controller incorrectly resets these registers upon FLR.
This causes PCISIG compliance FLR test to fail. Hence preventing
all functions from advertising FLR support if flag quirk_disable_flr
is set.
Link: https://lore.kernel.org/r/1635165075-89864-1-git-send-email-pthombar@cadence.com
Signed-off-by: Parshuram Thombare <pthombar@cadence.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Diffstat (limited to 'drivers/pci/controller/cadence/pcie-cadence.c')
0 files changed, 0 insertions, 0 deletions