diff options
| author | Karthikeyan Periyasamy <periyasa@codeaurora.org> | 2021-02-16 09:16:17 +0200 |
|---|---|---|
| committer | Kalle Valo <kvalo@codeaurora.org> | 2021-02-17 11:32:44 +0200 |
| commit | 480a73610c95511e42fb7d0359b523f66883e51a (patch) | |
| tree | 7cc6b371f6306dc1c0fa4e7eaf4b35fe671b9334 /drivers/net/wireless/ath/ath11k/hal.h | |
| parent | a233811ef60081192a2b13ce23253671114308d8 (diff) | |
| download | linux-480a73610c95511e42fb7d0359b523f66883e51a.tar.bz2 | |
ath11k: add static window support for register access
Three window slots can be configure. First window slot
dedicate for dynamic selection and remaining two slots
dedicate for static selection. To optimise the window
selection, frequent registers (UMAC, CE) are configure
in static window slot. so that we minimise the window
selection. Other registers are configure in dynamic window
slot. Get the window start address from the respective
offset and access the read/write register.
Tested-on: QCN9074 hw1.0 PCI WLAN.HK.2.4.0.1.r2-00012-QCAHKSWPL_SILICONZ-1
Signed-off-by: Karthikeyan Periyasamy <periyasa@codeaurora.org>
Signed-off-by: Anilkumar Kolli <akolli@codeaurora.org>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/1612946530-28504-7-git-send-email-akolli@codeaurora.org
Diffstat (limited to 'drivers/net/wireless/ath/ath11k/hal.h')
| -rw-r--r-- | drivers/net/wireless/ath/ath11k/hal.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/net/wireless/ath/ath11k/hal.h b/drivers/net/wireless/ath/ath11k/hal.h index 1f1b29cd0aa3..3f5687ebe1fc 100644 --- a/drivers/net/wireless/ath/ath11k/hal.h +++ b/drivers/net/wireless/ath/ath11k/hal.h @@ -39,6 +39,7 @@ struct ath11k_base; #define HAL_SHADOW_REG(x) (HAL_SHADOW_BASE_ADDR + (4 * (x))) /* WCSS Relative address */ +#define HAL_SEQ_WCSS_UMAC_OFFSET 0x00a00000 #define HAL_SEQ_WCSS_UMAC_REO_REG 0x00a38000 #define HAL_SEQ_WCSS_UMAC_TCL_REG 0x00a44000 #define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG 0x00a00000 @@ -47,6 +48,9 @@ struct ath11k_base; #define HAL_SEQ_WCSS_UMAC_CE1_DST_REG 0x00a03000 #define HAL_SEQ_WCSS_UMAC_WBM_REG 0x00a34000 +#define HAL_CE_WFSS_CE_REG_BASE 0x01b80000 +#define HAL_WLAON_REG_BASE 0x01f80000 + /* SW2TCL(x) R0 ring configuration address */ #define HAL_TCL1_RING_CMN_CTRL_REG 0x00000014 #define HAL_TCL1_RING_DSCP_TID_MAP 0x0000002c |