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| author | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2022-08-16 15:32:55 -0400 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2022-08-31 10:49:53 -0700 |
| commit | 3f0dadd230cc2630202a977fe52cd1dd7a7579a7 (patch) | |
| tree | 1073100bab060975491e43cb8e37b5f3cd7b7c45 /drivers/net/wan/pci200syn.c | |
| parent | 568035b01cfb107af8d2e4bd2fb9aea22cf5b868 (diff) | |
| download | linux-3f0dadd230cc2630202a977fe52cd1dd7a7579a7.tar.bz2 | |
clk: mediatek: clk-mt8195-vdo0: Set rate on vdo0_dp_intf0_dp_intf's parent
Add the CLK_SET_RATE_PARENT flag to the CLK_VDO0_DP_INTF0_DP_INTF
clock: this is required to trigger clock source selection on
CLK_TOP_EDP, while avoiding to manage the enablement of the former
separately from the latter in the displayport driver.
Fixes: 70282c90d4a2 ("clk: mediatek: Add MT8195 vdosys0 clock support")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220816193257.658487-2-nfraprado@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/net/wan/pci200syn.c')
0 files changed, 0 insertions, 0 deletions