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authorSteen Hegelund <steen.hegelund@microchip.com>2021-06-11 14:54:53 +0200
committerDavid S. Miller <davem@davemloft.net>2021-06-12 13:08:58 -0700
commit21e0c59edc09ff8d50722071ded66574b1cc4e99 (patch)
tree3816201fb5c8f8476f73cf26150b5d714aa53cf0 /drivers/net/phy
parent452d2c6fbae2c11e3b0c17a3afe7b145db2196e7 (diff)
downloadlinux-21e0c59edc09ff8d50722071ded66574b1cc4e99.tar.bz2
net: phylink: Add 25G BASE-R support
Add 25gbase-r interface type and speed to phylink. This is needed for the Sparx5 switch. Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/phy')
-rw-r--r--drivers/net/phy/phylink.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index bb9eeb74f70a..8ce8db487596 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -312,6 +312,11 @@ static int phylink_parse_mode(struct phylink *pl, struct fwnode_handle *fwnode)
phylink_set(pl->supported, 5000baseT_Full);
break;
+ case PHY_INTERFACE_MODE_25GBASER:
+ phylink_set(pl->supported, 25000baseCR_Full);
+ phylink_set(pl->supported, 25000baseKR_Full);
+ phylink_set(pl->supported, 25000baseSR_Full);
+ fallthrough;
case PHY_INTERFACE_MODE_USXGMII:
case PHY_INTERFACE_MODE_10GKR:
case PHY_INTERFACE_MODE_10GBASER: