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| author | Alex Elder <elder@linaro.org> | 2022-11-02 17:11:33 -0500 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2022-11-04 10:16:53 +0000 |
| commit | 1d8f16dbdf3693cae7567806cb1fb714fd1bcc70 (patch) | |
| tree | a01a049e1599db221465f12fe0d949b7f2d0f1a0 /drivers/net/ipa/ipa_endpoint.c | |
| parent | 6337b147828b4e3e893bde16dca8d4b6654d11c1 (diff) | |
| download | linux-1d8f16dbdf3693cae7567806cb1fb714fd1bcc70.tar.bz2 | |
net: ipa: add a parameter to aggregation registers
Starting with IPA v5.0, a single IPA instance can have more than 32
endpoints defined. To handle this, each register that holds a
bitmap of IPA endpoints is replicated as needed to represent the
available endpoints.
To prepare for this, registers that represent endpoint IDs in a bit
mask will be defined to have a parameter, with a stride value of 4
bytes. The first 32 endpoints are represented in the first 32-bit
register, then the next (up to) 32 endpoints at an offset 4 bytes
higher. When accessing such a register, the endpoint ID divided
by 32 determines the offset, and the endpoint ID modulo 32 defines
the endpoint's bit position within the register.
The first two registers we'll update for this are STATE_AGGR_ACTIVE
and AGGR_FORCE_CLOSE.
Until more than 32 endpoints are supported, this change has no
practical effect.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ipa/ipa_endpoint.c')
| -rw-r--r-- | drivers/net/ipa/ipa_endpoint.c | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/drivers/net/ipa/ipa_endpoint.c b/drivers/net/ipa/ipa_endpoint.c index 2a6184ea8f5c..32559ed498c1 100644 --- a/drivers/net/ipa/ipa_endpoint.c +++ b/drivers/net/ipa/ipa_endpoint.c @@ -350,29 +350,35 @@ ipa_endpoint_program_delay(struct ipa_endpoint *endpoint, bool enable) static bool ipa_endpoint_aggr_active(struct ipa_endpoint *endpoint) { - u32 mask = BIT(endpoint->endpoint_id); + u32 endpoint_id = endpoint->endpoint_id; + u32 mask = BIT(endpoint_id % 32); struct ipa *ipa = endpoint->ipa; + u32 unit = endpoint_id / 32; const struct ipa_reg *reg; u32 val; + /* This works until we actually have more than 32 endpoints */ WARN_ON(!(mask & ipa->available)); reg = ipa_reg(ipa, STATE_AGGR_ACTIVE); - val = ioread32(ipa->reg_virt + ipa_reg_offset(reg)); + val = ioread32(ipa->reg_virt + ipa_reg_n_offset(reg, unit)); return !!(val & mask); } static void ipa_endpoint_force_close(struct ipa_endpoint *endpoint) { - u32 mask = BIT(endpoint->endpoint_id); + u32 endpoint_id = endpoint->endpoint_id; + u32 mask = BIT(endpoint_id % 32); struct ipa *ipa = endpoint->ipa; + u32 unit = endpoint_id / 32; const struct ipa_reg *reg; + /* This works until we actually have more than 32 endpoints */ WARN_ON(!(mask & ipa->available)); reg = ipa_reg(ipa, AGGR_FORCE_CLOSE); - iowrite32(mask, ipa->reg_virt + ipa_reg_offset(reg)); + iowrite32(mask, ipa->reg_virt + ipa_reg_n_offset(reg, unit)); } /** |