diff options
| author | Jiri Pirko <jiri@nvidia.com> | 2020-09-15 11:40:56 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2020-09-15 15:57:16 -0700 |
| commit | 191c0c22b5c7acbe9670442293951229952fe677 (patch) | |
| tree | 2d668faf6a32c2274b433f3e89eb618cda32c4b6 /drivers/net/ethernet | |
| parent | 6ddac9dcb14dd31e8cef977ad73b7d07f9f665c8 (diff) | |
| download | linux-191c0c22b5c7acbe9670442293951229952fe677.tar.bz2 | |
mlxsw: reg: Add Monitoring FW General Debug Register
Introduce MFGD register that is used to configure firmware debugging.
Signed-off-by: Jiri Pirko <jiri@nvidia.com>
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet')
| -rw-r--r-- | drivers/net/ethernet/mellanox/mlxsw/reg.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h index f53761114f5a..421f02eac20f 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/reg.h +++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h @@ -9821,6 +9821,26 @@ static inline void mlxsw_reg_mtptptp_pack(char *payload, mlxsw_reg_mtptpt_message_type_set(payload, message_type); } +/* MFGD - Monitoring FW General Debug Register + * ------------------------------------------- + */ +#define MLXSW_REG_MFGD_ID 0x90F0 +#define MLXSW_REG_MFGD_LEN 0x0C + +MLXSW_REG_DEFINE(mfgd, MLXSW_REG_MFGD_ID, MLXSW_REG_MFGD_LEN); + +/* reg_mfgd_fw_fatal_event_mode + * 0 - don't check FW fatal (default) + * 1 - check FW fatal - enable MFDE trap + * Access: RW + */ +MLXSW_ITEM32(reg, mfgd, fatal_event_mode, 0x00, 9, 2); + +/* reg_mfgd_trigger_test + * Access: WO + */ +MLXSW_ITEM32(reg, mfgd, trigger_test, 0x00, 11, 1); + /* MGPIR - Management General Peripheral Information Register * ---------------------------------------------------------- * MGPIR register allows software to query the hardware and @@ -11071,6 +11091,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { MLXSW_REG(mtpppc), MLXSW_REG(mtpptr), MLXSW_REG(mtptpt), + MLXSW_REG(mfgd), MLXSW_REG(mgpir), MLXSW_REG(mfde), MLXSW_REG(tngcr), |