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authorIdo Schimmel <idosch@mellanox.com>2020-07-15 11:27:23 +0300
committerJakub Kicinski <kuba@kernel.org>2020-07-15 18:09:59 -0700
commitfbf0f5d185343300a80aa0fd8e633a985b9947e9 (patch)
treec23200cd473881cc5c2fe1132fc4591c155fb8bd /drivers/net/ethernet/mellanox/mlxsw/reg.h
parent5e126e7c4e52754e3aac0fbc5325abcbe1629388 (diff)
downloadlinux-fbf0f5d185343300a80aa0fd8e633a985b9947e9.tar.bz2
mlxsw: reg: Add policer bandwidth limits
Add policer bandwidth limits for both rate and burst size so that they could be enforced by a later patch. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Reviewed-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Petr Machata <petrm@mellanox.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'drivers/net/ethernet/mellanox/mlxsw/reg.h')
-rw-r--r--drivers/net/ethernet/mellanox/mlxsw/reg.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h
index 408003520602..3c5b25495751 100644
--- a/drivers/net/ethernet/mellanox/mlxsw/reg.h
+++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h
@@ -3405,11 +3405,20 @@ MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4);
*/
MLXSW_ITEM64(reg, qpcr, violate_count, 0x20, 0, 64);
+/* Packets */
#define MLXSW_REG_QPCR_LOWEST_CIR 1
#define MLXSW_REG_QPCR_HIGHEST_CIR (2 * 1000 * 1000 * 1000) /* 2Gpps */
#define MLXSW_REG_QPCR_LOWEST_CBS 4
#define MLXSW_REG_QPCR_HIGHEST_CBS 24
+/* Bandwidth */
+#define MLXSW_REG_QPCR_LOWEST_CIR_BITS 1024 /* bps */
+#define MLXSW_REG_QPCR_HIGHEST_CIR_BITS 2000000000000ULL /* 2Tbps */
+#define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP1 4
+#define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP2 4
+#define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP1 25
+#define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP2 31
+
static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid,
enum mlxsw_reg_qpcr_ir_units ir_units,
bool bytes, u32 cir, u16 cbs)