diff options
| author | Florian Fainelli <f.fainelli@gmail.com> | 2021-10-22 09:17:03 -0700 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2021-10-24 13:42:28 +0100 |
| commit | 3cd92eae9104a3dc1aa3a2de020e801061b947af (patch) | |
| tree | 32e9c6c1484e27c3259920affc7a7a14dc34e3b6 /drivers/net/ethernet/broadcom/genet/bcmmii.c | |
| parent | f4b054d9bb2b165296fbf4524f386d5b8a4aa455 (diff) | |
| download | linux-3cd92eae9104a3dc1aa3a2de020e801061b947af.tar.bz2 | |
net: bcmgenet: Add support for 7712 16nm internal EPHY
The 16nm internal EPHY that is present in 7712 is actually a 16nm
Gigabit PHY which has been forced to operate in 10/100 mode. Its
controls are therefore via the EXT_GPHY_CTRL registers and not via the
EXT_EPHY_CTRL which are used for all GENETv5 adapters. Add a match on
the 7712 compatible string to allow that differentiation to happen.
On previous GENETv4 chips the EXT_CFG_IDDQ_GLOBAL_PWR bit was cleared by
default, but this is not the case with this chip, so we need to make
sure we clear it to power on the EPHY.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/broadcom/genet/bcmmii.c')
| -rw-r--r-- | drivers/net/ethernet/broadcom/genet/bcmmii.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/net/ethernet/broadcom/genet/bcmmii.c b/drivers/net/ethernet/broadcom/genet/bcmmii.c index ad56f54eda0a..5f259641437a 100644 --- a/drivers/net/ethernet/broadcom/genet/bcmmii.c +++ b/drivers/net/ethernet/broadcom/genet/bcmmii.c @@ -139,14 +139,15 @@ void bcmgenet_phy_power_set(struct net_device *dev, bool enable) u32 reg = 0; /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */ - if (GENET_IS_V4(priv)) { + if (GENET_IS_V4(priv) || priv->ephy_16nm) { reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL); if (enable) { reg &= ~EXT_CK25_DIS; bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); mdelay(1); - reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN); + reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | + EXT_CFG_IDDQ_GLOBAL_PWR); reg |= EXT_GPHY_RESET; bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); mdelay(1); @@ -154,7 +155,7 @@ void bcmgenet_phy_power_set(struct net_device *dev, bool enable) reg &= ~EXT_GPHY_RESET; } else { reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | - EXT_GPHY_RESET; + EXT_GPHY_RESET | EXT_CFG_IDDQ_GLOBAL_PWR; bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); mdelay(1); reg |= EXT_CK25_DIS; |