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authorSivaprakash Murugesan <sivaprak@codeaurora.org>2020-06-12 13:28:16 +0530
committerMiquel Raynal <miquel.raynal@bootlin.com>2020-06-26 08:35:10 +0200
commitcb272395dceef1652247dad08a50ed4153ffbd43 (patch)
tree56e4e3eb12f7f773e2ce81c8556b4190822d209e /drivers/mtd
parent443440cc4a901af462239d286cd10721aa1c7dfc (diff)
downloadlinux-cb272395dceef1652247dad08a50ed4153ffbd43.tar.bz2
mtd: rawnand: qcom: set BAM mode only if not set already
BAM is DMA controller on QCOM ipq platforms, BAM mode on NAND driver is set by writing BAM_MODE_EN bit on NAND_CTRL register. NAND_CTRL is an operational register and in BAM mode operational registers are read only. So, before enabling BAM mode by writing the NAND_CTRL register, check if BAM mode was already enabled by the bootloader, and enable BAM mode only if it is not enabled already. Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/1591948696-16015-3-git-send-email-sivaprak@codeaurora.org
Diffstat (limited to 'drivers/mtd')
-rw-r--r--drivers/mtd/nand/raw/qcom_nandc.c11
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
index 78b5f211598c..bd7a7251429b 100644
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -2784,7 +2784,16 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
/* enable ADM or BAM DMA */
if (nandc->props->is_bam) {
nand_ctrl = nandc_read(nandc, NAND_CTRL);
- nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
+
+ /*
+ *NAND_CTRL is an operational registers, and CPU
+ * access to operational registers are read only
+ * in BAM mode. So update the NAND_CTRL register
+ * only if it is not in BAM mode. In most cases BAM
+ * mode will be enabled in bootloader
+ */
+ if (!(nand_ctrl & BAM_MODE_EN))
+ nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
} else {
nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
}