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| author | Sudip Mukherjee <sudip.mukherjee@sifive.com> | 2022-09-20 19:48:08 +0100 |
|---|---|---|
| committer | Tudor Ambarus <tudor.ambarus@microchip.com> | 2022-11-22 08:19:01 +0200 |
| commit | 1799cd8540b67b88514c82f5fae1c75b986bcbd8 (patch) | |
| tree | 61c473d8b542c33617752cb4ba3dc2594deac8e1 /drivers/mtd/spi-nor/core.h | |
| parent | a30f53d8bc0f9b55b4e8eea0e17b68cfd1f07f34 (diff) | |
| download | linux-1799cd8540b67b88514c82f5fae1c75b986bcbd8.tar.bz2 | |
mtd: spi-nor: add SFDP fixups for Quad Page Program
SFDP table of some flash chips do not advertise support of Quad Input
Page Program even though it has support. Use flags and add hardware
cap for these chips.
Signed-off-by: Sudip Mukherjee <sudip.mukherjee@sifive.com>
[tudor.ambarus@microchip.com: move pp setting in spi_nor_init_default_params]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20220920184808.44876-2-sudip.mukherjee@sifive.com
Diffstat (limited to 'drivers/mtd/spi-nor/core.h')
| -rw-r--r-- | drivers/mtd/spi-nor/core.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index ef0a73dbf348..f03b55cf7e6f 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -458,6 +458,7 @@ struct spi_nor_fixups { * SPI_NOR_NO_ERASE: no erase command needed. * NO_CHIP_ERASE: chip does not support chip erase. * SPI_NOR_NO_FR: can't do fastread. + * SPI_NOR_QUAD_PP: flash supports Quad Input Page Program. * * @no_sfdp_flags: flags that indicate support that can be discovered via SFDP. * Used when SFDP tables are not defined in the flash. These @@ -507,6 +508,7 @@ struct flash_info { #define SPI_NOR_NO_ERASE BIT(6) #define NO_CHIP_ERASE BIT(7) #define SPI_NOR_NO_FR BIT(8) +#define SPI_NOR_QUAD_PP BIT(9) u8 no_sfdp_flags; #define SPI_NOR_SKIP_SFDP BIT(0) |