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authorJungseung Lee <js07.lee@samsung.com>2020-03-18 21:06:14 +0900
committerTudor Ambarus <tudor.ambarus@microchip.com>2020-03-24 11:47:42 +0200
commit05635c14a292de0e1a221dc31c04aba3913f03c8 (patch)
tree0ba072883421d983b78f4d99c381d834093911fb /drivers/mtd/spi-nor/core.h
parent2d284768b49bcf1c643c08a201ff2161041178ef (diff)
downloadlinux-05635c14a292de0e1a221dc31c04aba3913f03c8.tar.bz2
mtd: spi-nor: Add SR 4bit block protection support
Currently we are supporting block protection only for flash chips with 3 block protection bits (BP0-2) in the SR register. Enable block protection support for flashes with 4 block protection bits (BP0-3). Add a flash_info flag for flashes that describe 4 block protection bits. Add another flash_info flag for flashes in which BP3 bit is not adjacent to the BP0-2 bits. Tested with a n25q512ax3 (BP0-3) and w25q128 (BP0-2). Signed-off-by: Jungseung Lee <js07.lee@samsung.com> Reviewed-by: Michael Walle <michael@walle.cc> Tested-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Diffstat (limited to 'drivers/mtd/spi-nor/core.h')
-rw-r--r--drivers/mtd/spi-nor/core.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 3ce826b35ad1..6f2f6b27173f 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -24,6 +24,8 @@ enum spi_nor_option_flags {
SNOR_F_HAS_16BIT_SR = BIT(9),
SNOR_F_NO_READ_CR = BIT(10),
SNOR_F_HAS_SR_TB_BIT6 = BIT(11),
+ SNOR_F_HAS_4BIT_BP = BIT(12),
+ SNOR_F_HAS_SR_BP3_BIT6 = BIT(13),
};
struct spi_nor_read_command {
@@ -301,6 +303,14 @@ struct flash_info {
* status register. Must be used with
* SPI_NOR_HAS_TB.
*/
+#define SPI_NOR_4BIT_BP BIT(17) /*
+ * Flash SR has 4 bit fields (BP0-3)
+ * for block protection.
+ */
+#define SPI_NOR_BP3_SR_BIT6 BIT(18) /*
+ * BP3 is bit 6 of status register.
+ * Must be used with SPI_NOR_4BIT_BP.
+ */
/* Part specific fixup hooks. */
const struct spi_nor_fixups *fixups;