diff options
| author | Pratyush Yadav <p.yadav@ti.com> | 2020-10-05 21:01:28 +0530 |
|---|---|---|
| committer | Vignesh Raghavendra <vigneshr@ti.com> | 2020-11-09 11:56:16 +0530 |
| commit | fb27f198971a68fec59d5493b68e35e916fce62c (patch) | |
| tree | 21e4ca1bf4746603b30d2bdfbb7435db61365ef2 /drivers/mtd/spi-nor/core.c | |
| parent | 0e1b2fc4e5f681ba716f5a50da710251c717413d (diff) | |
| download | linux-fb27f198971a68fec59d5493b68e35e916fce62c.tar.bz2 | |
mtd: spi-nor: sfdp: parse xSPI Profile 1.0 table
This table is indication that the flash is xSPI compliant and hence
supports octal DTR mode. Extract information like the fast read opcode,
dummy cycles, the number of dummy cycles needed for a Read Status
Register command, and the number of address bytes needed for a Read
Status Register command.
We don't know what speed the controller is running at. Find the fast
read dummy cycles for the fastest frequency the flash can run at to be
sure we are never short of dummy cycles. If nothing is available,
default to 20. Flashes that use a different value should update it in
their fixup hooks.
Since we want to set read settings, expose spi_nor_set_read_settings()
in core.h.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20201005153138.6437-6-p.yadav@ti.com
Diffstat (limited to 'drivers/mtd/spi-nor/core.c')
| -rw-r--r-- | drivers/mtd/spi-nor/core.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 3cd025d79a98..fea619802825 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2332,7 +2332,7 @@ static int spi_nor_check(struct spi_nor *nor) return 0; } -static void +void spi_nor_set_read_settings(struct spi_nor_read_command *read, u8 num_mode_clocks, u8 num_wait_states, |