diff options
| author | Boris Brezillon <bbrezillon@kernel.org> | 2020-03-13 19:42:43 +0000 |
|---|---|---|
| committer | Tudor Ambarus <tudor.ambarus@microchip.com> | 2020-03-17 09:28:03 +0200 |
| commit | acb96ecd59f7fdd8b2791f225d101dfdc2ab38a9 (patch) | |
| tree | 6c135fd15c670ce4cf3a8c2cfb5c128aea6e39b8 /drivers/mtd/spi-nor/core.c | |
| parent | 893218a8e828648989f2257f2a6c95ae04a37f7c (diff) | |
| download | linux-acb96ecd59f7fdd8b2791f225d101dfdc2ab38a9.tar.bz2 | |
mtd: spi-nor: Move GigaDevice bits out of core.c
Create a SPI NOR manufacturer driver for GigaDevice chips, and move the
GigaDevice definitions outside of core.c.
Signed-off-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Diffstat (limited to 'drivers/mtd/spi-nor/core.c')
| -rw-r--r-- | drivers/mtd/spi-nor/core.c | 60 |
1 files changed, 1 insertions, 59 deletions
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 3850c638f95a..236632d15c42 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2054,21 +2054,6 @@ static struct spi_nor_fixups mx25l25635_fixups = { .post_bfpt = mx25l25635_post_bfpt_fixups, }; -static void gd25q256_default_init(struct spi_nor *nor) -{ - /* - * Some manufacturer like GigaDevice may use different - * bit to set QE on different memories, so the MFR can't - * indicate the quad_enable method for this case, we need - * to set it in the default_init fixup hook. - */ - nor->params.quad_enable = spi_nor_sr1_bit6_quad_enable; -} - -static struct spi_nor_fixups gd25q256_fixups = { - .default_init = gd25q256_default_init, -}; - /* NOTE: double check command sets and memory organization when you add * more nor chips. This current list focusses on newer chips, which * have been converging on command sets which including JEDEC ID. @@ -2081,50 +2066,6 @@ static struct spi_nor_fixups gd25q256_fixups = { * old entries may be missing 4K flag. */ static const struct flash_info spi_nor_ids[] = { - /* GigaDevice */ - { - "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) - }, - { - "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) - }, - { - "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) - }, - { - "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) - }, - { - "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) - }, - { - "gd25lq128d", INFO(0xc86018, 0, 64 * 1024, 256, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) - }, - { - "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) - }, - { - "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512, - SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | - SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | - SPI_NOR_TB_SR_BIT6) - .fixups = &gd25q256_fixups, - }, - /* Intel/Numonyx -- xxxs33b */ { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) }, { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) }, @@ -2430,6 +2371,7 @@ static const struct spi_nor_manufacturer *manufacturers[] = { &spi_nor_esmt, &spi_nor_everspin, &spi_nor_fujitsu, + &spi_nor_gigadevice, }; static const struct flash_info * |