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authorMasahiro Yamada <yamada.masahiro@socionext.com>2018-06-23 01:06:38 +0900
committerMiquel Raynal <miquel.raynal@bootlin.com>2018-07-18 09:24:14 +0200
commit1dfac31a5a63ac04a9b5fbc3f5105a586560f191 (patch)
treee186e6351b8f56d2f58ec0dbda6d4b0d9e43b1de /drivers/mtd/nand/raw/denali_pci.c
parent6f1fe97bec349a1fd6c5a8c7c5998d759fe721d5 (diff)
downloadlinux-1dfac31a5a63ac04a9b5fbc3f5105a586560f191.tar.bz2
mtd: rawnand: denali: optimize timing parameters for data interface
This commit improves the ->setup_data_interface() hook. The denali_setup_data_interface() needs the frequency of clk_x and the ratio of clk_x / clk. The latter is currently hardcoded in the driver, like this: #define DENALI_CLK_X_MULT 6 The IP datasheet requires that clk_x / clk be 4, 5, or 6. I just chose 6 because it is the most defensive value, but it is not optimal. By getting the clock rate of both "clk" and "clk_x", the driver can compute the timing values more precisely. To not break the existing platforms, the fallback value, 50 MHz is provided. It is true for all upstreamed platforms. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Richard Weinberger <richard@nod.at> Tested-by: Richard Weinberger <richard@nod.at> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Diffstat (limited to 'drivers/mtd/nand/raw/denali_pci.c')
-rw-r--r--drivers/mtd/nand/raw/denali_pci.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/mtd/nand/raw/denali_pci.c b/drivers/mtd/nand/raw/denali_pci.c
index 49cb3e1f8bd0..7c8efc4c7bdf 100644
--- a/drivers/mtd/nand/raw/denali_pci.c
+++ b/drivers/mtd/nand/raw/denali_pci.c
@@ -73,6 +73,7 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
denali->irq = dev->irq;
denali->ecc_caps = &denali_pci_ecc_caps;
denali->nand.ecc.options |= NAND_ECC_MAXIMIZE;
+ denali->clk_rate = 50000000; /* 50 MHz */
denali->clk_x_rate = 200000000; /* 200 MHz */
ret = pci_request_regions(dev, DENALI_NAND_NAME);