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authorMiquel Raynal <miquel.raynal@bootlin.com>2020-08-27 10:51:58 +0200
committerMiquel Raynal <miquel.raynal@bootlin.com>2020-09-28 15:59:42 +0200
commitbace41f80f65dc4ba13c892bac783e7e81847379 (patch)
tree16b44ea42a23ec7ce4b826e54b7626576e98dfb0 /drivers/mtd/nand/raw/cadence-nand-controller.c
parentef24f97daac4d9450c956ab165d8337c2feca0e9 (diff)
downloadlinux-bace41f80f65dc4ba13c892bac783e7e81847379.tar.bz2
mtd: rawnand: Use the new ECC engine type enumeration
Mechanical switch from the legacy "mode" enumeration to the new "engine type" enumeration in drivers and board files. The device tree parsing is also updated to return the new enumeration from the old strings. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/linux-mtd/20200827085208.16276-11-miquel.raynal@bootlin.com
Diffstat (limited to 'drivers/mtd/nand/raw/cadence-nand-controller.c')
-rw-r--r--drivers/mtd/nand/raw/cadence-nand-controller.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/mtd/nand/raw/cadence-nand-controller.c b/drivers/mtd/nand/raw/cadence-nand-controller.c
index 71516af85f23..db29e5e512df 100644
--- a/drivers/mtd/nand/raw/cadence-nand-controller.c
+++ b/drivers/mtd/nand/raw/cadence-nand-controller.c
@@ -2611,7 +2611,7 @@ static int cadence_nand_attach_chip(struct nand_chip *chip)
chip->bbt_options |= NAND_BBT_USE_FLASH;
chip->bbt_options |= NAND_BBT_NO_OOB;
- chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
chip->options |= NAND_NO_SUBPAGE_WRITE;
@@ -2757,7 +2757,7 @@ static int cadence_nand_chip_init(struct cdns_nand_ctrl *cdns_ctrl,
* Default to HW ECC engine mode. If the nand-ecc-mode property is given
* in the DT node, this entry will be overwritten in nand_scan_ident().
*/
- chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
ret = nand_scan(chip, cdns_chip->nsels);
if (ret) {