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authorLinus Torvalds <torvalds@linux-foundation.org>2016-08-02 17:05:11 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2016-08-02 17:05:11 -0400
commitaffe8a2abd0d7815bb2653eea2717d0e0f8ac7e3 (patch)
tree913838395d0480fcf310030d12714439cfb0e4ba /drivers/mtd/devices
parent44cee85a8824464e7e951e590243c2a85d79c494 (diff)
parent1dcff2e4ae728a36876bdb108173f4cbcae128bf (diff)
downloadlinux-affe8a2abd0d7815bb2653eea2717d0e0f8ac7e3.tar.bz2
Merge tag 'for-linus-20160801' of git://git.infradead.org/linux-mtd
Pull MTD updates from Brian Norris: "NAND: Quoting Boris: 'This pull request contains only one notable change: - Addition of the MTK NAND controller driver And a bunch of specific NAND driver improvements/fixes. Here are the changes that are worth mentioning: - A few fixes/improvements for the xway NAND controller driver - A few fixes for the sunxi NAND controller driver - Support for DMA in the sunxi NAND driver - Support for the sunxi NAND controller IP embedded in A23/A33 SoCs - Addition for bitflips detection in erased pages to the brcmnand driver - Support for new brcmnand IPs - Update of the OMAP-GPMC binding to support DMA channel description' In addition, some small fixes around error handling, etc., as well as one long-standing corner case issue (2.6.20, I think?) with writing 1 byte less than a page. NOR: - rework some error handling on reads and writes, so we can better handle (for instance) SPI controllers which have limitations on their maximum transfer size - add new Cadence Quad SPI flash controller driver - add new Atmel QSPI flash controller driver - add new Hisilicon SPI flash controller driver - support a few new flash, and update supported features on others - fix the logic used for detecting a fully-unlocked flash And other miscellaneous small fixes" * tag 'for-linus-20160801' of git://git.infradead.org/linux-mtd: (60 commits) mtd: spi-nor: don't build Cadence QuadSPI on non-ARM mtd: mtk-nor: remove duplicated include from mtk-quadspi.c mtd: nand: fix bug writing 1 byte less than page size mtd: update description of MTD_BCM47XXSFLASH symbol mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller mtd: spi-nor: Bindings for Cadence Quad SPI Flash Controller driver mtd: nand: brcmnand: Change BUG_ON in brcmnand_send_cmd mtd: pmcmsp-flash: Allocating too much in init_msp_flash() mtd: maps: sa1100-flash: potential NULL dereference mtd: atmel-quadspi: add driver for Atmel QSPI controller mtd: nand: omap2: fix return value check in omap_nand_probe() Documentation: atmel-quadspi: add binding file for Atmel QSPI driver mtd: spi-nor: add hisilicon spi-nor flash controller driver mtd: spi-nor: support dual, quad, and WP for Gigadevice mtd: spi-nor: Added support for n25q00a. memory: Update dependency of IFC for Layerscape mtd: nand: jz4780: Update MODULE_AUTHOR email address mtd: nand: sunxi: prevent a small memory leak mtd: nand: sunxi: add reset line support mtd: nand: sunxi: update DT bindings ...
Diffstat (limited to 'drivers/mtd/devices')
-rw-r--r--drivers/mtd/devices/Kconfig16
-rw-r--r--drivers/mtd/devices/m25p80.c37
2 files changed, 26 insertions, 27 deletions
diff --git a/drivers/mtd/devices/Kconfig b/drivers/mtd/devices/Kconfig
index 64a248556d29..58329d2dacd1 100644
--- a/drivers/mtd/devices/Kconfig
+++ b/drivers/mtd/devices/Kconfig
@@ -113,12 +113,12 @@ config MTD_SST25L
if you want to specify device partitioning.
config MTD_BCM47XXSFLASH
- tristate "R/O support for serial flash on BCMA bus"
+ tristate "Support for serial flash on BCMA bus"
depends on BCMA_SFLASH && (MIPS || ARM)
help
BCMA bus can have various flash memories attached, they are
registered by bcma as platform devices. This enables driver for
- serial flash memories (only read-only mode is implemented).
+ serial flash memories.
config MTD_SLRAM
tristate "Uncached system RAM"
@@ -171,18 +171,6 @@ config MTDRAM_ERASE_SIZE
as a module, it is also possible to specify this as a parameter when
loading the module.
-#If not a module (I don't want to test it as a module)
-config MTDRAM_ABS_POS
- hex "SRAM Hexadecimal Absolute position or 0"
- depends on MTD_MTDRAM=y
- default "0"
- help
- If you have system RAM accessible by the CPU but not used by Linux
- in normal operation, you can give the physical address at which the
- available RAM starts, and the MTDRAM driver will use it instead of
- allocating space from Linux's available memory. Otherwise, leave
- this set to zero. Most people will want to leave this as zero.
-
config MTD_BLOCK2MTD
tristate "MTD using block device"
depends on BLOCK
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index 9d6854467651..9cf7fcd28034 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -73,14 +73,15 @@ static int m25p80_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
return spi_write(spi, flash->command, len + 1);
}
-static void m25p80_write(struct spi_nor *nor, loff_t to, size_t len,
- size_t *retlen, const u_char *buf)
+static ssize_t m25p80_write(struct spi_nor *nor, loff_t to, size_t len,
+ const u_char *buf)
{
struct m25p *flash = nor->priv;
struct spi_device *spi = flash->spi;
struct spi_transfer t[2] = {};
struct spi_message m;
int cmd_sz = m25p_cmdsz(nor);
+ ssize_t ret;
spi_message_init(&m);
@@ -98,9 +99,14 @@ static void m25p80_write(struct spi_nor *nor, loff_t to, size_t len,
t[1].len = len;
spi_message_add_tail(&t[1], &m);
- spi_sync(spi, &m);
+ ret = spi_sync(spi, &m);
+ if (ret)
+ return ret;
- *retlen += m.actual_length - cmd_sz;
+ ret = m.actual_length - cmd_sz;
+ if (ret < 0)
+ return -EIO;
+ return ret;
}
static inline unsigned int m25p80_rx_nbits(struct spi_nor *nor)
@@ -119,21 +125,21 @@ static inline unsigned int m25p80_rx_nbits(struct spi_nor *nor)
* Read an address range from the nor chip. The address range
* may be any size provided it is within the physical boundaries.
*/
-static int m25p80_read(struct spi_nor *nor, loff_t from, size_t len,
- size_t *retlen, u_char *buf)
+static ssize_t m25p80_read(struct spi_nor *nor, loff_t from, size_t len,
+ u_char *buf)
{
struct m25p *flash = nor->priv;
struct spi_device *spi = flash->spi;
struct spi_transfer t[2];
struct spi_message m;
unsigned int dummy = nor->read_dummy;
+ ssize_t ret;
/* convert the dummy cycles to the number of bytes */
dummy /= 8;
if (spi_flash_read_supported(spi)) {
struct spi_flash_read_message msg;
- int ret;
memset(&msg, 0, sizeof(msg));
@@ -149,8 +155,9 @@ static int m25p80_read(struct spi_nor *nor, loff_t from, size_t len,
msg.data_nbits = m25p80_rx_nbits(nor);
ret = spi_flash_read(spi, &msg);
- *retlen = msg.retlen;
- return ret;
+ if (ret < 0)
+ return ret;
+ return msg.retlen;
}
spi_message_init(&m);
@@ -165,13 +172,17 @@ static int m25p80_read(struct spi_nor *nor, loff_t from, size_t len,
t[1].rx_buf = buf;
t[1].rx_nbits = m25p80_rx_nbits(nor);
- t[1].len = len;
+ t[1].len = min(len, spi_max_transfer_size(spi));
spi_message_add_tail(&t[1], &m);
- spi_sync(spi, &m);
+ ret = spi_sync(spi, &m);
+ if (ret)
+ return ret;
- *retlen = m.actual_length - m25p_cmdsz(nor) - dummy;
- return 0;
+ ret = m.actual_length - m25p_cmdsz(nor) - dummy;
+ if (ret < 0)
+ return -EIO;
+ return ret;
}
/*