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authorRenius Chen <reniuschengl@gmail.com>2021-01-11 16:22:49 +0800
committerUlf Hansson <ulf.hansson@linaro.org>2021-02-01 11:54:46 +0100
commitc58c5950b87a5ba8270c15a86b4261800e4079c1 (patch)
treeca6c93df41e6ecb9dc74310a7f07db6267bc0096 /drivers/mmc
parentffd68f356e411f79d5d448908a1f60e374c95cb2 (diff)
downloadlinux-c58c5950b87a5ba8270c15a86b4261800e4079c1.tar.bz2
mmc: sdhci-pci-gli: Finetune HS400 RX delay for GL9763E
To improve the compatibility of GL9763E with HS400 eMMC cards, finetune the RX delay of HS400 mode. Signed-off-by: Renius Chen <reniuschengl@gmail.com> Link: https://lore.kernel.org/r/20210111082249.17092-1-reniuschengl@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/host/sdhci-pci-gli.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
index fb14f70cb9a0..4a0f69b97a78 100644
--- a/drivers/mmc/host/sdhci-pci-gli.c
+++ b/drivers/mmc/host/sdhci-pci-gli.c
@@ -95,6 +95,10 @@
#define PCIE_GLI_9763E_MMC_CTRL 0x960
#define GLI_9763E_HS400_SLOW BIT(3)
+#define PCIE_GLI_9763E_CLKRXDLY 0x934
+#define GLI_9763E_HS400_RXDLY GENMASK(31, 28)
+#define GLI_9763E_HS400_RXDLY_5 0x5
+
#define SDHCI_GLI_9763E_CQE_BASE_ADDR 0x200
#define GLI_9763E_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \
SDHCI_TRNS_BLK_CNT_EN | \
@@ -802,6 +806,11 @@ static void gli_set_gl9763e(struct sdhci_pci_slot *slot)
value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MAX);
pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value);
+ pci_read_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, &value);
+ value &= ~GLI_9763E_HS400_RXDLY;
+ value |= FIELD_PREP(GLI_9763E_HS400_RXDLY, GLI_9763E_HS400_RXDLY_5);
+ pci_write_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, value);
+
pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
value &= ~GLI_9763E_VHS_REV;
value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R);