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| author | Anton Vorontsov <avorontsov@ru.mvista.com> | 2009-03-17 00:14:00 +0300 |
|---|---|---|
| committer | Pierre Ossman <drzeus@drzeus.cx> | 2009-03-24 21:30:10 +0100 |
| commit | 3e3bf20756aeee57a40fd37b923263c9a51b8c68 (patch) | |
| tree | 9cf64169c61208b59a1a6c16e0bfc48b45a1c7a7 /drivers/mmc/host/sdhci.h | |
| parent | 8114634ccb54d67a8c01e5825d95bff4e7f7b357 (diff) | |
| download | linux-3e3bf20756aeee57a40fd37b923263c9a51b8c68.tar.bz2 | |
sdhci: Add quirk for controllers that need small delays for PIO
Small udelay is needed to make eSDHC work in PIO mode. Without
the delay reading causes endless interrupt storm, and writing
corrupts data. The first guess would be that we must wait for
some bit in some register, but I didn't find any reliable bits
that change before and after the delay.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
Diffstat (limited to 'drivers/mmc/host/sdhci.h')
| -rw-r--r-- | drivers/mmc/host/sdhci.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index b9bc622735ba..c5ce9ee1a1bc 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -220,6 +220,8 @@ struct sdhci_host { #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16) /* Controller has nonstandard clock management */ #define SDHCI_QUIRK_NONSTANDARD_CLOCK (1<<17) +/* Controller does not like fast PIO transfers */ +#define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18) int irq; /* Device IRQ */ void __iomem * ioaddr; /* Mapped address */ |