diff options
| author | Shirley Her (SC) <shirley.her@bayhubtech.com> | 2019-08-21 18:38:30 +0000 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2019-09-11 15:58:39 +0200 |
| commit | 9674bab490d6c33989fa9eb08604beedd215f3ac (patch) | |
| tree | 66a5c8453f848781804c386cd8ba80b2d5129638 /drivers/mmc/host/sdhci-pci-o2micro.c | |
| parent | c894e33ddc1910e14d6f2a2016f60ab613fd8b37 (diff) | |
| download | linux-9674bab490d6c33989fa9eb08604beedd215f3ac.tar.bz2 | |
mmc: sdhci-pci-o2micro: Change O2 Host PLL and DLL register name
Change O2 Host PLL and DLL register name
Signed-off-by: Shirley Her <shirley.her@bayhubtech.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc/host/sdhci-pci-o2micro.c')
| -rw-r--r-- | drivers/mmc/host/sdhci-pci-o2micro.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-pci-o2micro.c index 9dc4548271b4..b3a33d9e974f 100644 --- a/drivers/mmc/host/sdhci-pci-o2micro.c +++ b/drivers/mmc/host/sdhci-pci-o2micro.c @@ -51,7 +51,7 @@ #define O2_SD_VENDOR_SETTING2 0x1C8 #define O2_SD_HW_TUNING_DISABLE BIT(4) -#define O2_PLL_WDT_CONTROL1 0x1CC +#define O2_PLL_DLL_WDT_CONTROL1 0x1CC #define O2_PLL_FORCE_ACTIVE BIT(18) #define O2_PLL_LOCK_STATUS BIT(14) #define O2_PLL_SOFT_RESET BIT(12) @@ -316,23 +316,23 @@ static void sdhci_o2_enable_internal_clock(struct sdhci_host *host) u32 scratch32; /* PLL software reset */ - scratch32 = sdhci_readl(host, O2_PLL_WDT_CONTROL1); + scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); scratch32 |= O2_PLL_SOFT_RESET; - sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1); + sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); udelay(1); scratch32 &= ~(O2_PLL_SOFT_RESET); - sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1); + sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); /* PLL force active */ scratch32 |= O2_PLL_FORCE_ACTIVE; - sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1); + sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); /* Wait max 20 ms */ timeout = ktime_add_ms(ktime_get(), 20); while (1) { bool timedout = ktime_after(ktime_get(), timeout); - scratch = sdhci_readw(host, O2_PLL_WDT_CONTROL1); + scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1); if (scratch & O2_PLL_LOCK_STATUS) break; if (timedout) { @@ -350,9 +350,9 @@ static void sdhci_o2_enable_internal_clock(struct sdhci_host *host) out: /* Cancel PLL force active */ - scratch32 = sdhci_readl(host, O2_PLL_WDT_CONTROL1); + scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); scratch32 &= ~O2_PLL_FORCE_ACTIVE; - sdhci_writel(host, scratch32, O2_PLL_WDT_CONTROL1); + sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1); } static int sdhci_o2_get_cd(struct mmc_host *mmc) |