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| author | Oded Gabbay <ogabbay@kernel.org> | 2022-06-24 18:56:42 +0300 |
|---|---|---|
| committer | Oded Gabbay <ogabbay@kernel.org> | 2022-07-12 09:09:27 +0300 |
| commit | 01d9ccf8657b54960862fb9db4bab5f73c766b47 (patch) | |
| tree | 761ff5d9c320c5d9edb5ae8d0bd51e1147876e3c /drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in4_slave_regs.h | |
| parent | ccf991e4f2205e98cfbb6e8f2d7b477bd378328f (diff) | |
| download | linux-01d9ccf8657b54960862fb9db4bab5f73c766b47.tar.bz2 | |
habanalabs/gaudi2: add asic registers header files
Add the relevant GAUDI2 ASIC registers header files. These files are
generated automatically from a tool maintained by the VLSI engineers.
There are more files which are not upstreamed because only very few
defines from those files are used in the driver. For those files, I
copied the relevant defines into gaudi2_regs.h and gaudi2_masks.h, to
reduce the size of this patch.
Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
Diffstat (limited to 'drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in4_slave_regs.h')
| -rw-r--r-- | drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in4_slave_regs.h | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in4_slave_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in4_slave_regs.h new file mode 100644 index 000000000000..5ace0f43cc78 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_mme_ctrl_lo_arch_agu_in4_slave_regs.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_REGS_H_ +#define ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_REGS_H_ + +/* + ***************************************** + * DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE + * (Prototype: MME_AGU_CORE) + ***************************************** + */ + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_0 0x40CB210 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_1 0x40CB214 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_2 0x40CB218 + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_3 0x40CB21C + +#define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_4 0x40CB220 + +#endif /* ASIC_REG_DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_REGS_H_ */ |