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authorBjorn Andersson <bjorn.andersson@linaro.org>2022-08-09 21:07:43 -0700
committerVinod Koul <vkoul@kernel.org>2022-08-30 11:01:23 +0530
commit5894ff12c7ec0bd5960c6f1d91b64674d9ffb9bf (patch)
treeb0dacb799c7720e648a49a66ee7166664bf99df1 /drivers/mfd/ucb1x00-core.c
parent317e00bbf950b5dd83f18f6771c3e402485052ea (diff)
downloadlinux-5894ff12c7ec0bd5960c6f1d91b64674d9ffb9bf.tar.bz2
phy: qcom: edp: Perform lane configuration
The TRANSCIEVER_BIAS_EN, HIGHZ_DRVR_EN and PHY_CFG_1 registers are used for lane configuration, with the currently hard coded configuration being a mix of 2 and 4 lane (effectively 2-lane). Properly implement lane configuration for 1, 2 and 4 lanes. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220810040745.3582985-4-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/mfd/ucb1x00-core.c')
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