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| author | Yong Wu <yong.wu@mediatek.com> | 2019-08-24 11:02:03 +0800 |
|---|---|---|
| committer | Joerg Roedel <jroedel@suse.de> | 2019-08-30 15:57:27 +0200 |
| commit | 15a01f4c60607ad888faf0386070181f9c97577f (patch) | |
| tree | 5b80191fb37489cd448157b12ce6ada7e0879172 /drivers/memory | |
| parent | 907ba6a195991adb2a3edf4aff0d8dbb308d4d97 (diff) | |
| download | linux-15a01f4c60607ad888faf0386070181f9c97577f.tar.bz2 | |
iommu/mediatek: Add mmu1 support
Normally the M4U HW connect EMI with smi. the diagram is like below:
EMI
|
M4U
|
smi-common
|
-----------------
| | | | ...
larb0 larb1 larb2 larb3
Actually there are 2 mmu cells in the M4U HW, like this diagram:
EMI
---------
| |
mmu0 mmu1 <- M4U
| |
---------
|
smi-common
|
-----------------
| | | | ...
larb0 larb1 larb2 larb3
This patch add support for mmu1. In order to get better performance,
we could adjust some larbs go to mmu1 while the others still go to
mmu0. This is controlled by a SMI COMMON register SMI_BUS_SEL(0x220).
mt2712, mt8173 and mt8183 M4U HW all have 2 mmu cells. the default
value of that register is 0 which means all the larbs go to mmu0
defaultly.
This is a preparing patch for adjusting SMI_BUS_SEL for mt8183.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'drivers/memory')
0 files changed, 0 insertions, 0 deletions