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| author | Joseph Lo <josephl@nvidia.com> | 2019-05-29 16:21:36 +0800 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2020-06-22 13:54:57 +0200 |
| commit | 10de21148f7d28c9e918aaee7cede74a7d506e24 (patch) | |
| tree | 1fbcf76bc4a6a561c49e6c3bcd4ed1bbe2a86d98 /drivers/memory/tegra/mc.h | |
| parent | 6cc8823ad3e85207dfb4c93f31dcdb05297d1b42 (diff) | |
| download | linux-10de21148f7d28c9e918aaee7cede74a7d506e24.tar.bz2 | |
memory: tegra: Add EMC scaling support code for Tegra210
This is the initial patch for Tegra210 EMC frequency scaling. It has the
code to program various aspects of the EMC that are standardized, but it
does not yet include the specific programming sequence needed for clock
scaling.
The driver is designed to support LPDDR4 SDRAM. Devices that use LPDDR4
need to perform training of the RAM before it can be used. Firmware will
perform this training during early boot and pass a table of supported
frequencies to the kernel via device tree.
For the frequencies above 800 MHz, periodic retraining is needed to
compensate for changes in timing. This periodic training will have to be
performed until the frequency drops back to or below 800 MHz.
This driver provides helpers used during this runtime retraining that
will be used by the sequence specific code in a follow-up patch.
Based on work by Peter De Schrijver <pdeschrijver@nvidia.com>.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/memory/tegra/mc.h')
| -rw-r--r-- | drivers/memory/tegra/mc.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index 957c6eb74ff9..afa3ba45c9e6 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -34,6 +34,7 @@ #define MC_EMEM_ARB_TIMING_W2W 0xbc #define MC_EMEM_ARB_TIMING_R2W 0xc0 #define MC_EMEM_ARB_TIMING_W2R 0xc4 +#define MC_EMEM_ARB_MISC2 0xc8 #define MC_EMEM_ARB_DA_TURNS 0xd0 #define MC_EMEM_ARB_DA_COVERS 0xd4 #define MC_EMEM_ARB_MISC0 0xd8 |