[media] v4l: ti-vpe: support loading of scaler coefficients

The SC block in VPE/VIP contains a SRAM within it. This internal memory
requires to be loaded with appropriate scaler coefficients from a contiguous
block of memory through VPDMA.

The horizontal and vertical scaler each require 2 sets of scaler coefficients
for luma and chroma scaling. The horizontal polyphase scaler requires
coefficients for a 32 phase and 8 tap filter. Similarly, the vertical scaler
requires coefficients for a 5 tap filter.

The choice of the scaler coefficients depends on the scaling ratio. Add
coefficient tables for different scaling ratios in sc_coeffs.h. In the case of
horizontal downscaling, we need to consider the change in ratio caused by
decimation performed by the horizontal scaler.

In order to load the scaler coefficients via VPDMA, a configuration descriptor
is used in block mode. The payload for the descriptor is the scaler coefficients
copied to memory. Coefficients for each phase have to be placed in memory in a
particular order understood by the scaler hardware.

The choice of the scaler coefficients, and the loading of the coefficients from
our tables to a contiguous buffer is managed by the functions
sc_set_hs_coefficients and sc_set_vs_coefficients.

The sc_data handle is now added with some parameters to describe the state of
the coefficients loaded in the SC block. 'loaded_coeff_h' and 'loaded_coeff_v'
hold the address of the last dma buffer which was used by VPDMA to copy
coefficients. This information can be used by a vpe mem-to-mem context to decide
whether it should load coefficients or not. 'hs_index' and 'vs_index' provide
some optimization by preventing loading of coefficients if the scaling ratio
didn't change between 2 contexts. 'load_coeff_h' and 'load_coeff_v' tell the
vpe/vip driver whether we need to load the coefficients through VPDMA or not.

Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>

1 files changed, 31 insertions, 0 deletions

diff --git a/drivers/media/platform/ti-vpe/sc.h b/drivers/media/platform/ti-vpe/sc.h
index 924854465c5d..c89f3d1a3bad 100644
--- a/drivers/media/platform/ti-vpe/sc.h
+++ b/drivers/media/platform/ti-vpe/sc.h
@@ -161,15 +161,46 @@
 #define CFG_OFF_W_MASK			0x07ff
 #define CFG_OFF_W_SHIFT			16
 
+/* number of phases supported by the polyphase scalers */
+#define SC_NUM_PHASES			32
+
+/* number of taps used by horizontal polyphase scaler */
+#define SC_H_NUM_TAPS			7
+
+/* number of taps used by vertical polyphase scaler */
+#define SC_V_NUM_TAPS			5
+
+/* number of taps expected by the scaler in it's coefficient memory */
+#define SC_NUM_TAPS_MEM_ALIGN		8
+
+/*
+ * coefficient memory size in bytes:
+ * num phases x num sets(luma and chroma) x num taps(aligned) x coeff size
+ */
+#define SC_COEF_SRAM_SIZE	(SC_NUM_PHASES * 2 * SC_NUM_TAPS_MEM_ALIGN * 2)
+
 struct sc_data {
 	void __iomem		*base;
 	struct resource		*res;
 
+	dma_addr_t		loaded_coeff_h; /* loaded h coeffs in SC */
+	dma_addr_t		loaded_coeff_v; /* loaded v coeffs in SC */
+
+	bool			load_coeff_h;	/* have new h SC coeffs */
+	bool			load_coeff_v;	/* have new v SC coeffs */
+
+	unsigned int		hs_index;	/* h SC coeffs selector */
+	unsigned int		vs_index;	/* v SC coeffs selector */
+
 	struct platform_device *pdev;
 };
 
 void sc_set_regs_bypass(struct sc_data *sc, u32 *sc_reg0);
 void sc_dump_regs(struct sc_data *sc);
+void sc_set_hs_coeffs(struct sc_data *sc, void *addr, unsigned int src_w,
+		unsigned int dst_w);
+void sc_set_vs_coeffs(struct sc_data *sc, void *addr, unsigned int src_h,
+		unsigned int dst_h);
 struct sc_data *sc_create(struct platform_device *pdev);
 
 #endif