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| author | Jason Gunthorpe <jgg@nvidia.com> | 2022-11-29 16:42:27 -0400 |
|---|---|---|
| committer | Jason Gunthorpe <jgg@nvidia.com> | 2022-12-02 12:04:39 -0400 |
| commit | 90337f526c98129b0b180fc52dc5f57d8e7a8614 (patch) | |
| tree | d7458a03027cde56b8191f656dc5cdf1531a767d /drivers/iommu | |
| parent | 169dd5c987e60e62aa5785b30d22ded2ae000286 (diff) | |
| parent | b7b275e60bcd5f89771e865a8239325f86d9927d (diff) | |
| download | linux-90337f526c98129b0b180fc52dc5f57d8e7a8614.tar.bz2 | |
Merge tag 'v6.1-rc7' into iommufd.git for-next
Resolve conflicts in drivers/vfio/vfio_main.c by using the iommfd version.
The rc fix was done a different way when iommufd patches reworked this
code.
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Diffstat (limited to 'drivers/iommu')
| -rw-r--r-- | drivers/iommu/intel/iommu.c | 8 | ||||
| -rw-r--r-- | drivers/iommu/intel/pasid.c | 5 |
2 files changed, 6 insertions, 7 deletions
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 157c97274110..ebe44a07c4b0 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -959,11 +959,9 @@ static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain, domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE); pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE; - if (domain_use_first_level(domain)) { - pteval |= DMA_FL_PTE_XD | DMA_FL_PTE_US; - if (iommu_is_dma_domain(&domain->domain)) - pteval |= DMA_FL_PTE_ACCESS; - } + if (domain_use_first_level(domain)) + pteval |= DMA_FL_PTE_XD | DMA_FL_PTE_US | DMA_FL_PTE_ACCESS; + if (cmpxchg64(&pte->val, 0ULL, pteval)) /* Someone else set it while we were thinking; use theirs. */ free_pgtable_page(tmp_page); diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c index 95d73f19ab61..fb3c7020028d 100644 --- a/drivers/iommu/intel/pasid.c +++ b/drivers/iommu/intel/pasid.c @@ -644,7 +644,7 @@ int intel_pasid_setup_second_level(struct intel_iommu *iommu, * Since it is a second level only translation setup, we should * set SRE bit as well (addresses are expected to be GPAs). */ - if (pasid != PASID_RID2PASID) + if (pasid != PASID_RID2PASID && ecap_srs(iommu->ecap)) pasid_set_sre(pte); pasid_set_present(pte); spin_unlock(&iommu->lock); @@ -687,7 +687,8 @@ int intel_pasid_setup_pass_through(struct intel_iommu *iommu, * We should set SRE bit as well since the addresses are expected * to be GPAs. */ - pasid_set_sre(pte); + if (ecap_srs(iommu->ecap)) + pasid_set_sre(pte); pasid_set_present(pte); spin_unlock(&iommu->lock); |