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authorWill Deacon <will.deacon@arm.com>2014-11-14 17:18:23 +0000
committerWill Deacon <will.deacon@arm.com>2015-01-19 14:46:44 +0000
commite1d3c0fd701df831169b116cd5c5d6203ac07f70 (patch)
treeeb2537042682bf45a36148d06bb0bfb10ce3da74 /drivers/iommu/io-pgtable.h
parentfdb1d7be7c4d452e9735aeb2b60ae8a2fcf0a514 (diff)
downloadlinux-e1d3c0fd701df831169b116cd5c5d6203ac07f70.tar.bz2
iommu: add ARM LPAE page table allocator
A number of IOMMUs found in ARM SoCs can walk architecture-compatible page tables. This patch adds a generic allocator for Stage-1 and Stage-2 v7/v8 long-descriptor page tables. 4k, 16k and 64k pages are supported, with up to 4-levels of walk to cover a 48-bit address space. Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'drivers/iommu/io-pgtable.h')
-rw-r--r--drivers/iommu/io-pgtable.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/iommu/io-pgtable.h b/drivers/iommu/io-pgtable.h
index fdd792c37698..05c4e593a25f 100644
--- a/drivers/iommu/io-pgtable.h
+++ b/drivers/iommu/io-pgtable.h
@@ -5,6 +5,10 @@
* Public API for use by IOMMU drivers
*/
enum io_pgtable_fmt {
+ ARM_32_LPAE_S1,
+ ARM_32_LPAE_S2,
+ ARM_64_LPAE_S1,
+ ARM_64_LPAE_S2,
IO_PGTABLE_NUM_FMTS,
};
@@ -47,6 +51,16 @@ struct io_pgtable_cfg {
/* Low-level data specific to the table format */
union {
+ struct {
+ u64 ttbr[2];
+ u64 tcr;
+ u64 mair[2];
+ } arm_lpae_s1_cfg;
+
+ struct {
+ u64 vttbr;
+ u64 vtcr;
+ } arm_lpae_s2_cfg;
};
};