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authorAndrea Merello <andrea.merello@gmail.com>2019-09-12 16:43:08 +0200
committerJonathan Cameron <Jonathan.Cameron@huawei.com>2019-09-21 18:15:10 +0100
commit348eb0b2c4f0f912d626fa789dfeb084b083e1f0 (patch)
tree2a4f85e0a6e631293ce8f8b5e8438d9dae4b1d07 /drivers/iio/adc/ad7949.c
parent0fe2f2b789190661df24bb8bf62294145729a1fe (diff)
downloadlinux-348eb0b2c4f0f912d626fa789dfeb084b083e1f0.tar.bz2
iio: ad7949: fix incorrect SPI xfer len
This driver supports 14-bits and 16-bits devices. All of them have a 14-bit configuration registers. All SPI trasfers, for reading AD conversion results and for writing the configuration register, fit in two bytes. The driver always uses 4-bytes xfers which seems at least pointless (maybe even harmful). This patch trims the SPI xfer len and the buffer size to two bytes. Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Reviewed-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Diffstat (limited to 'drivers/iio/adc/ad7949.c')
-rw-r--r--drivers/iio/adc/ad7949.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/iio/adc/ad7949.c b/drivers/iio/adc/ad7949.c
index 518044c31a73..5c2b3446fa4a 100644
--- a/drivers/iio/adc/ad7949.c
+++ b/drivers/iio/adc/ad7949.c
@@ -54,7 +54,7 @@ struct ad7949_adc_chip {
u8 resolution;
u16 cfg;
unsigned int current_channel;
- u32 buffer ____cacheline_aligned;
+ u16 buffer ____cacheline_aligned;
};
static int ad7949_spi_write_cfg(struct ad7949_adc_chip *ad7949_adc, u16 val,
@@ -67,7 +67,7 @@ static int ad7949_spi_write_cfg(struct ad7949_adc_chip *ad7949_adc, u16 val,
struct spi_transfer tx[] = {
{
.tx_buf = &ad7949_adc->buffer,
- .len = 4,
+ .len = 2,
.bits_per_word = bits_per_word,
},
};
@@ -95,7 +95,7 @@ static int ad7949_spi_read_channel(struct ad7949_adc_chip *ad7949_adc, int *val,
struct spi_transfer tx[] = {
{
.rx_buf = &ad7949_adc->buffer,
- .len = 4,
+ .len = 2,
.bits_per_word = bits_per_word,
},
};