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authorAlex Deucher <alexander.deucher@amd.com>2020-02-12 01:46:16 -0500
committerAlex Deucher <alexander.deucher@amd.com>2020-02-14 12:58:58 -0500
commitc657b936ea98630ef5ba4f130ab1ad5c534d0165 (patch)
tree5217d9cb284e639cda721b1451104895d4ed3722 /drivers/gpu
parentaad4e2dbe543bc1633bc208ac7bddc4f0bb185ba (diff)
downloadlinux-c657b936ea98630ef5ba4f130ab1ad5c534d0165.tar.bz2
drm/amdgpu/soc15: fix xclk for raven
It's 25 Mhz (refclk / 4). This fixes the interpretation of the rlc clock counter. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/soc15.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 15f3424a1ff7..2b488dfb2f21 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -272,7 +272,12 @@ static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
static u32 soc15_get_xclk(struct amdgpu_device *adev)
{
- return adev->clock.spll.reference_freq;
+ u32 reference_clock = adev->clock.spll.reference_freq;
+
+ if (adev->asic_type == CHIP_RAVEN)
+ return reference_clock / 4;
+
+ return reference_clock;
}