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authorYongqiang Sun <yongqiang.sun@amd.com>2019-06-25 19:08:50 -0400
committerAlex Deucher <alexander.deucher@amd.com>2019-08-15 10:52:46 -0500
commit9d19c73f37473bfc4c9216e5e48b4684cc2050d2 (patch)
treee2a9098a6192b43ed7cff748747ebf4100700593 /drivers/gpu
parent99a423418aeabe9a572b3e5194f2c06180a066fb (diff)
downloadlinux-9d19c73f37473bfc4c9216e5e48b4684cc2050d2.tar.bz2
drm/amd/display: Add DFS reference clock field
Add to clk_mgr_internal struct, for future use. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
index 4b5505fa980c..213046de1675 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
@@ -216,6 +216,8 @@ struct clk_mgr_internal {
bool dfs_bypass_enabled;
/* True if the DFS-bypass feature is enabled and active. */
bool dfs_bypass_active;
+
+ uint32_t dfs_ref_freq_khz;
/*
* Cache the display clock returned by VBIOS if DFS-bypass is enabled.
* This is basically "Crystal Frequency In KHz" (XTALIN) frequency