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| author | Huang Rui <ray.huang@amd.com> | 2022-05-17 14:58:41 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-06-03 16:44:15 -0400 |
| commit | 8763e4c1a0e6710dccb8fccba96fcd6caaa50cae (patch) | |
| tree | a0f44fec5aa00c086557d3fbdf1094e6f86aba75 /drivers/gpu | |
| parent | 10c4ad3ae025dd0e343a09d2ea4b0e71f8d10797 (diff) | |
| download | linux-8763e4c1a0e6710dccb8fccba96fcd6caaa50cae.tar.bz2 | |
drm/amdgpu/pm: update MP v13_0_4 smu message register marco
Update MP v13_0_4 register macro for SMU message
v2: squash in missed case (Alex)
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c index 5de7da75d14a..5215ead4978f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c @@ -51,6 +51,15 @@ #define mmMP1_SMN_C2PMSG_90 0x029a #define mmMP1_SMN_C2PMSG_90_BASE_IDX 0 +#define mmMP1_SMN_C2PMSG_66_V13_0_4 0x0282 +#define mmMP1_SMN_C2PMSG_66_V13_0_4_BASE_IDX 1 + +#define mmMP1_SMN_C2PMSG_82_V13_0_4 0x0292 +#define mmMP1_SMN_C2PMSG_82_V13_0_4_BASE_IDX 1 + +#define mmMP1_SMN_C2PMSG_90_V13_0_4 0x029a +#define mmMP1_SMN_C2PMSG_90_V13_0_4_BASE_IDX 1 + /* SMU 13.0.5 has its specific mailbox messaging registers */ #define mmMP1_C2PMSG_2 (0xbee142 + 0xb00000 / 4) @@ -92,6 +101,8 @@ static void smu_cmn_read_arg(struct smu_context *smu, if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5)) *arg = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_34); + else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4)) + *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82_V13_0_4); else *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); } @@ -141,6 +152,8 @@ static u32 __smu_cmn_poll_stat(struct smu_context *smu) for ( ; timeout > 0; timeout--) { if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5)) reg = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_33); + else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4)) + reg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90_V13_0_4); else reg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); if ((reg & MP1_C2PMSG_90__CONTENT_MASK) != 0) @@ -167,6 +180,9 @@ static void __smu_cmn_reg_print_error(struct smu_context *smu, if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 5)) { msg_idx = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_2); prm = RREG32_SOC15(MP1, 0, mmMP1_C2PMSG_34); + } else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4)) { + msg_idx = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66_V13_0_4); + prm = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82_V13_0_4); } else { msg_idx = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66); prm = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); @@ -268,6 +284,10 @@ static void __smu_cmn_send_msg(struct smu_context *smu, WREG32_SOC15(MP1, 0, mmMP1_C2PMSG_33, 0); WREG32_SOC15(MP1, 0, mmMP1_C2PMSG_34, param); WREG32_SOC15(MP1, 0, mmMP1_C2PMSG_2, msg); + } else if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4)) { + WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90_V13_0_4, 0); + WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82_V13_0_4, param); + WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66_V13_0_4, msg); } else { WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, param); |