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authorRex Zhu <Rex.Zhu@amd.com>2018-01-16 16:00:02 +0800
committerAlex Deucher <alexander.deucher@amd.com>2018-02-19 14:17:54 -0500
commit59fc8cde739bc81464d214b23fd717f24608eb75 (patch)
treee03f380553ea6cb0b908a08f31b656745eba0718 /drivers/gpu
parentee85c07abe0f9899c4d18796bc2d6b90aa7ad4af (diff)
downloadlinux-59fc8cde739bc81464d214b23fd717f24608eb75.tar.bz2
drm/amd/pp: Move DPMTABLE_* definitions to common header file
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h5
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h6
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h11
3 files changed, 11 insertions, 11 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
index beba25cb2b07..8d4e9c193b8b 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
@@ -34,11 +34,6 @@
#define SMU7_VOLTAGE_CONTROL_BY_SVID2 0x2
#define SMU7_VOLTAGE_CONTROL_MERGED 0x3
-#define DPMTABLE_OD_UPDATE_SCLK 0x00000001
-#define DPMTABLE_OD_UPDATE_MCLK 0x00000002
-#define DPMTABLE_UPDATE_SCLK 0x00000004
-#define DPMTABLE_UPDATE_MCLK 0x00000008
-
enum gpu_pt_config_reg_type {
GPU_CONFIGREG_MMR = 0,
GPU_CONFIGREG_SMC_IND,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
index 689fe9f5e0b8..ab3e8798bee8 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
@@ -189,12 +189,6 @@ struct vega10_vbios_boot_state {
uint32_t dcef_clock;
};
-#define DPMTABLE_OD_UPDATE_SCLK 0x00000001
-#define DPMTABLE_OD_UPDATE_MCLK 0x00000002
-#define DPMTABLE_UPDATE_SCLK 0x00000004
-#define DPMTABLE_UPDATE_MCLK 0x00000008
-#define DPMTABLE_OD_UPDATE_VDDC 0x00000010
-
struct vega10_smc_state_table {
uint32_t soc_boot_level;
uint32_t gfx_boot_level;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
index d6772a8f242d..6f528e662a6f 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
@@ -358,6 +358,17 @@ struct phm_clocks {
uint32_t clock[MAX_NUM_CLOCKS];
};
+#define DPMTABLE_OD_UPDATE_SCLK 0x00000001
+#define DPMTABLE_OD_UPDATE_MCLK 0x00000002
+#define DPMTABLE_UPDATE_SCLK 0x00000004
+#define DPMTABLE_UPDATE_MCLK 0x00000008
+#define DPMTABLE_OD_UPDATE_VDDC 0x00000010
+
+/* To determine if sclk and mclk are in overdrive state */
+#define SCLK_OVERDRIVE_ENABLED 0x00000001
+#define MCLK_OVERDRIVE_ENABLED 0x00000002
+#define VDDC_OVERDRIVE_ENABLED 0x00000010
+
struct phm_odn_performance_level {
uint32_t clock;
uint32_t vddc;